Abstract: A communication apparatus including: a receiving portion that receives alignment specifying information, the alignment specifying information indicating which of main memories included in a first information processing apparatus and a second information processing apparatus to align the requested data; a division location calculating portion that calculates a divisional location of the requested data so that the divisional location of the requested data becomes an alignment boundary on the main memory included in any one of the first and the second information processing apparatuses specified by the received alignment specifying information, the alignment boundary being integral multiples of a given data width; and a transmitting portion that divides the requested data stored into the main memory in the second information processing apparatus based on the calculated divisional location, and transmits the divided data to the first information processing apparatus.

Abstract: In a parallel computer system including a plurality of processors, processors are classified into a plurality of groups including a prescribed number of processors, and processors are connected to each other in a complete connecting manner in the groups. Those groups are connected to each other as the respective processors are connected in linear to each other.

Abstract: A computer cluster arranged at a lattice point in a lattice-like interconnection network contains four nodes and an internal communication network. Two nodes can transmit packets to adjacent computer clusters located along the X direction, and the two other nodes can transmit packets to adjacent computer clusters located along the Y direction. Each node directly transmits a packet to an adjacent computer cluster in the direction in which the node can transmit packets, when the destination of the packet is located in the direction. When the destination of a packet to be transmitted from a node is not located in the direction in which the receiving node can transmit packets, the node transfers the packet to one of the other nodes through the internal communication network for transmitting the packet to the destination of the packet through the one of the other nodes.

Abstract: A network interface device is provided. The network interface device is connected to a computer and performs communications via a network includes a first management unit that identifies a communication connection by a port number, and manages a communication connection state of each port by a context that is stored in a storage unit and is associated with a port number, a second management unit that manages a storage state of the context, and a control unit that refers to the context, and performs an exemplary operation to establish a communication connection and an exemplary operation to cut off a communication connection between ports.

Abstract: When allocating an unallocated queued job, by using a CDA having a mesh structure to which active jobs are allocated, a job scheduling apparatus scans an event list that includes information about allocation events and release events for jobs, determines the coordinates and the time at which submeshes corresponding to the queued jobs are reserved, and arranges the submeshes by overlapping them on the CDA.

Abstract: A system has a plurality of nodes connected in a multi-dimensional matrix and having node addresses, respectively, each of the nodes having a processor, and a router for transmitting a request packet to a node adjacent to its own node located in n+1th dimension when the address of nth dimension of its own node is matched to the address of nth dimension of the target node, transmitting a response packet to a node adjacent to its own node located in nth dimension when the address of n+1th dimension of its own node is matched to the address of n+1th dimension of the response packet, wherein the router terminates a request packet when the address of the request packet is fully matched to the node address of its own node in all the dimensions, transfers the data conveyed by the request packet to the processor of its own node for processing.

Abstract: An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.

Abstract: A barrier synchronization apparatus includes a receiving device which transmits a first synchronization signal to a synchronization device when the first synchronization signal in which a transmission destination is set in advance according to setting conditions including an algorithm of the barrier synchronization and an execution condition is received. A synchronization device synchronizes n first synchronization signals which are set in advance according to the setting conditions, wherein n is a positive integer, and designates transmission of m second synchronization signals in which transmission destinations are set in advance according to the setting conditions after the synchronization is established, wherein m is a positive integer. A transmitting device transmits the second synchronization signals to m transmission destinations set in advance, when a transmission designation information indicating the transmission designation is received from the synchronization device.

Abstract: A system has a transmitter for transmitting a sequence of packets, the transmitter has a first counter for storing a first sequence number, a first generating unit for generating an error check code for checking an error in each of the packets on the basis of the header and the data in each of the packets and the first sequence number, and a transmitting unit for transmitting each of the packet together with each of the error check code and a receiver has a second counter for storing a second sequence number, a second generating unit for generating an error check code for checking an error in each of the packets on the basis of the header and the data in each of the packets received from the transmitter and the second sequence number and an error check unit for checking an error in the sequence of the packet.

Abstract: A packet processing device for effectively assembling packets. A packet accumulator stores received packets. A packet analyzer extracts, from the packets, analysis information about flows to which the packets belong. A frequency predictor calculates a frequency prediction value based on the reception interval of packets belonging to an identical flow, and stores the calculated value in a frequency prediction storage. Also, in response to input of the analysis information, the frequency predictor reads the corresponding frequency prediction value and sends the read value to a flow processor. The flow processor generates flow information on the flow corresponding to the analysis information, and analyzes the generated flow information and those stored in a flow information storage, to select an assembling termination flow based on the frequency prediction values. A packet transfer unit reads the packets corresponding to the selected flow from the packet accumulator and transfers the packets to a host.

Abstract: A header processing unit divides each received packet into a header section and a data section. Adapter memory stores each packet. A packet reassembly processing unit generates a new header, based on the header section of each of the plurality of packets and notifies a host computer of the new header and a plurality of pieces of location information indicating the storage position of each of a plurality of data sections stored in the adapter memory. A DMA control unit reads the plurality of data sections from the adapter memory, according to a transfer instruction generated in the host computer, using the location information and transfers it to the host computer.

Abstract: A computer cluster arranged at a lattice point in a lattice-like interconnection network contains four nodes and an internal communication network. Two nodes can transmit packets to adjacent computer clusters located along the X direction, and the two other nodes can transmit packets to adjacent computer clusters located along the Y direction. Each node directly transmits a packet to an adjacent computer cluster in the direction in which the node can transmit packets, when the destination of the packet is located in the direction. When the destination of a packet to be transmitted from a node is not located in the direction in which the receiving node can transmit packets, the node transfers the packet to one of the other nodes through the internal communication network for transmitting the packet to the destination of the packet through the one of the other nodes.

Abstract: A packet processing device for effectively assembling packets. A packet accumulator stores received packets. A packet analyzer extracts, from the packets, analysis information about flows to which the packets belong. A frequency predictor calculates a frequency prediction value based on the reception interval of packets belonging to an identical flow, and stores the calculated value in a frequency prediction storage. Also, in response to input of the analysis information, the frequency predictor reads the corresponding frequency prediction value and sends the read value to a flow processor. The flow processor generates flow information on the flow corresponding to the analysis information, and analyzes the generated flow information and those stored in a flow information storage, to select an assembling termination flow based on the frequency prediction values. A packet transfer unit reads the packets corresponding to the selected flow from the packet accumulator and transfers the packets to a host.

Abstract: The present invention has been made to provide a computer management program, a managed computer control program, a computer management apparatus, a managed computer, a computer management system, a computer management method, and a managed computer control method allowing the management agent to easily perform autonomous communication frequency control.

Abstract: A header processing unit divides each received packet into a header section and a data section. Adapter memory stores each packet. A packet reassembly processing unit generates a new header, based on the header section of each of the plurality of packets and notifies a host computer of the new header and a plurality of pieces of location information indicating the storage position of each of a plurality of data sections stored in the adapter memory. A DMA control unit reads the plurality of data sections from the adapter memory, according to a transfer instruction generated in the host computer, using the location information and transfers it to the host computer.

Abstract: An in-order state queue holds store tags as in-order information about store instructions. A temporal store cache, which uses store addresses as indexes, holds store tags and store values. A first retrieving unit retrieves store tags preceding a load tag. A second retrieving unit compares the store tag read from the temporal store cache according to the address for the load instruction with the store tag from the first retrieving unit and, when they coincide with each other, outputs a hit signal.

Abstract: An in-order state queue holds store tags as in-order information about store instructions. A temporal store cache, which uses store addresses as indexes, holds store tags and store values. A first retrieving unit retrieves store tags preceding a load tag. A second retrieving unit compares the store tag read from the temporal store cache according to the address for the load instruction with the store tag from the first retrieving unit and, when they coincide with each other, outputs a hit signal.