Patents by Inventor Yuichiro Egi

Yuichiro Egi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040132262
    Abstract: A solid-state imaging device comprises: unit cells in matrix where rows and columns of them are arranged in an upper surface of a semiconductor substrate, each of the unit cells including a photodiode that develops a certain level of signal charge in response to an amount of incident light and accumulates the signal charge, and a readout circuit for reading the signal charge from the photodiode, interlayer films laid over the semiconductor substrate and having wiring layers provided therein, light shield film formed over the interlayer films and having an aperture provided right above the photodiode in each of the unit cells, trains of first light shield upright barrier walls located in a space between two adjacent unit cells arranged in the same column, and trains of second light shield upright barrier walls located in a space between the adjacent unit cells in the same row, the first and second light shield upright barrier walls being embedded in the interlayer films between the semiconductor substrate and
    Type: Application
    Filed: September 4, 2003
    Publication date: July 8, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ayabe, Hirofumi Yamashita, Ikuko Inoue, Yuichiro Egi
  • Patent number: 6335250
    Abstract: In a method of manufacturing a semiconductor device, gate electrodes are formed on a surface of a silicon substrate, and, over the surface of the silicon substrate thus formed, an amorphous silicon film is formed by deposition. Next, the amorphous silicon film is selectively grown to form single-crystalline film portions. Then, a resist is formed only on an interconnection formation portion. Thereafter, the amorphous silicon film portions and other than the amorphous silicon film portion which lies in the interconnection formation portion are removed. Then, a local interconnection layer comprised of a silicide film is formed the region of the amorphous silicon film portion lying in the interconnection formation portion and the regions of the single-crystalline silicon film portions. According to the above-mentioned manufacturing method, the step of forming the local interconnection layer is simplified which step was complicated in case of the conventional technique.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: January 1, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuichiro Egi