Patents by Inventor Yuichiro HANAFUSA

Yuichiro HANAFUSA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9952924
    Abstract: A memory device has a plurality of memory units, an error correction processor, and a memory controller. The memory units include semiconductor memories, and read and write in parallel. The error correction processor converts input content data into recording data which includes the content data and an error correction code. The error correction processor decodes the content data by performing conversion including error correction of recording data read out of the memory units. The memory controller writes recording data divided into a number of data into an area of areas extending over the memory units. The memory controller reads the divided recording data from the area. The memory controller determines that writing into the area has been completed normally if the number of the semiconductor memories of which abnormality has been detected is less than or equal to a number of abnormalities correctable by the error correction processor.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuichiro Hanafusa
  • Publication number: 20170170848
    Abstract: According to one embodiment, a video server device includes: a memory; and a memory controller. The memory controller includes: a first ECC encoding unit configured to add a first ECC code to each of first data units of the data block, each of the first data units written to memory chips in parallel; a second ECC encoding unit configured to add a second ECC code to each of second data units of the data block, each of the second data units written to the respective memory chips; a second decoding unit configured to perform, based on the second ECC code, a second error correction on each of the second data units of the data block; and a first decoding unit configured to perform, based on the first ECC code, a first error correction on each of the first data units of the data block.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 15, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yuichiro HANAFUSA
  • Publication number: 20160203046
    Abstract: A memory device of embodiments has a plurality of memory units, an error correction processor, and a memory controller. Each of the memory units has semiconductor memories, and writes in parallel and reads in parallel. The error correction processor converts input content data into recording data which includes the content data and, an error correction code. The error correction processor decodes the content data by performing conversion including error correction with respect to the recording data read out of the memory units. The memory controller writes recording data, which has been divided into a predetermined number of data, into an area of areas extending over the memory units. The memory controller reads the divided recording data out of the area.
    Type: Application
    Filed: April 18, 2014
    Publication date: July 14, 2016
    Inventor: Yuichiro HANAFUSA
  • Patent number: 8966168
    Abstract: An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided pieces of data and monitoring a read request and a buffer full notice, in a case where the number of read requests does not reach the number of valid memory units and the buffer full notice continues in all buffers except for one buffer which does not output the read request, performing a read control corresponding to the buffers which output the buffer full notice, and performing control of the integration of a piece of data reconstructed, after being read from the memory unit corresponding to the buffer which does not output the read request and the pieces of data read from the memory units corresponding to the buffers which output the buffer full notice.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuichiro Hanafusa
  • Publication number: 20130304967
    Abstract: An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided pieces of data and monitoring a read request and a buffer full notice, in a case where the number of read requests does not reach the number of valid memory units and the buffer full notice continues in all buffers except for one buffer which does not output the read request, performing a read control corresponding to the buffers which output the buffer full notice, and performing control of the integration of a piece of data reconstructed, after being read from the memory unit corresponding to the buffer which does not output the read request and the pieces of data read from the memory units corresponding to the buffers which output the buffer full notice.
    Type: Application
    Filed: January 23, 2013
    Publication date: November 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yuichiro HANAFUSA