Abstract: The present invention provides a solid state image sensor and a camera using such a solid state image sensor, in which all of stage registers of the shift register can be reset efficiently without increasing the number of pads and/or sensor pins. The solid state image sensor comprises a plurality of photoelectric conversion elements 31 arranged in a two-dimensional array, a vertical shift register 503 disposed in a column direction and a horizontal shift register 504 disposed in a row direction and is characterized in that a timing for controlling resetting means for a first stage register of the shift register differs from a timing for controlling a second stage register and subsequent stage registers. Further, as a concrete example, the second stage register and subsequent stage registers are rest by a pulse for driving the shift register and the first stage register is reset by a pulse in which a high level is reached only upon power ON.

Abstract: An image sensor includes a plurality of operation circuits. The operation circuit operates pixel signals read out from a group of pixels included in a readout area to generate a pixel signal in the thinning readout mode. A plurality of column selecting switches are arranged between the output terminals of the plurality of operation circuits and a plurality of output channels. A control circuit controls the plurality of column selecting switches such that pixel signals the number of which is equal to the number of the plurality of output channels are output to the plurality of output channels in parallel in the thinning readout mode. The circuit arrangements, each included in the corresponding one of the plurality of operation circuits and each viewed from the corresponding one of the column selecting switches used in the thinning readout mode, are equivalent to each other.

Abstract: An image sensor has a plurality of pixels arrayed to form a plurality of columns. The sensor includes a plurality of readout circuits which generate pixel signals based on signals supplied from the pixels of respective columns, a plurality of output channels, a plurality of column selecting switches, and a control circuit which controls the plurality of column selecting switches. The control circuit controls the plurality of column selecting switches so as to output the pixel signals of target readout pixels to output channels selected based on a selection rule in the spatial order of the pixels in the full pixel readout mode. The control circuit controls the plurality of column selecting switches so as to output the thinned-out pixel signals of target readout areas to output channels selected based on the same rule as the selection rule in the spatial order of the areas in the thinning readout mode.

Abstract: The present invention provides a solid state image sensor and a camera using such a solid state image sensor, in which all of stage registers of the shift register can be reset efficiently without increasing the number of pads and/or sensor pins. The solid state image sensor comprises a plurality of photoelectric conversion elements 31 arranged in a two-dimensional array, a vertical shift register 503 disposed in a column direction and a horizontal shift register 504 disposed in a row direction and is characterized in that a timing for controlling resetting means for a first stage register of the shift register differs from a timing for controlling a second stage register and subsequent stage registers. Further, as a concrete example, the second stage register and subsequent stage registers are rest by a pulse for driving the shift register and the first stage register is reset by a pulse in which a high level is reached only upon power ON.

Abstract: The present invention provides a solid state image sensor and a camera using such a solid state image sensor, in which all of stage registers of the shift register can be reset efficiently without increasing the number of pads and/or sensor pins. The solid state image sensor comprises a plurality of photoelectric conversion elements 31 arranged in a two-dimensional array, a vertical shift register 503 disposed in a column direction and a horizontal shift register 504 disposed in a row direction and is characterized in that a timing for controlling resetting means for a first stage register of the shift register differs from a timing for controlling a second stage register and subsequent stage registers. Further, as a concrete example, the second stage register and subsequent stage registers are rest by a pulse for driving the shift register and the first stage register is reset by a pulse in which a high level is reached only upon power ON.

Abstract: An image sensor includes a plurality of operation circuits. The operation circuit operates pixel signals read out from a group of pixels included in a readout area to generate a pixel signal in the thinning readout mode. A plurality of column selecting switches are arranged between the output terminals of the plurality of operation circuits and a plurality of output channels. A control circuit controls the plurality of column selecting switches such that pixel signals the number of which is equal to the number of the plurality of output channels are output to the plurality of output channels in parallel in the thinning readout mode. The circuit arrangements, each included in the corresponding one of the plurality of operation circuits and each viewed from the corresponding one of the column selecting switches used in the thinning readout mode, are equivalent to each other.

Abstract: An image sensor has a plurality of pixels arrayed to form a plurality of columns. The sensor includes a plurality of readout circuits which generate pixel signals based on signals supplied from the pixels of respective columns, a plurality of output channels, a plurality of column selecting switches, and a control circuit which controls the plurality of column selecting switches. The control circuit controls the plurality of column selecting switches so as to output the pixel signals of target readout pixels to output channels selected based on a selection rule in the spatial order of the pixels in the full pixel readout mode. The control circuit controls the plurality of column selecting switches so as to output the thinned-out pixel signals of target readout areas to output channels selected based on the same rule as the selection rule in the spatial order of the areas in the thinning readout mode.

Abstract: The present invention provides a solid state image sensor and a camera using such a solid state image sensor, in which all of stage registers of the shift register can be reset efficiently without increasing the number of pads and/or sensor pins. The solid state image sensor comprises a plurality of photoelectric conversion elements 31 arranged in a two-dimensional array, a vertical shift register 503 disposed in a column direction and a horizontal shift register 504 disposed in a row direction and is characterized in that a timing for controlling resetting means for a first stage register of the shift register differs from a timing for controlling a second stage register and subsequent stage registers. Further, as a concrete example, the second stage register and subsequent stage registers are rest by a pulse for driving the shift register and the first stage register is reset by a pulse in which a high level is reached only upon power ON.