Abstract: Provided is a semiconductor memory device that is capable of accurately detecting a retention failure of a memory cell. The semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.

Abstract: There is provided a semiconductor storage device in which memory cells can easily be set at a proper potential in standby mode, along with a reduction in the area of circuitry for controlling the potential of source lines of memory cells. A semiconductor storage device includes static-type memory cells and a control circuit. The control circuit includes a first switching transistor provided between a source line being coupled to a source electrode of driving transistors and a first voltage, a second switching transistor provided in parallel with the first switching transistor, and a source line potential control circuit which makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line in standby mode.