Patents by Inventor Yujeong Shim
Yujeong Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002795Abstract: A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contacts that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board. An assembly includes the pluggable processor module and a printed circuit board assembly (“PCBA”) including a module aperture that is large enough to receive the power board and narrower than the capacitor board.Type: GrantFiled: April 13, 2022Date of Patent: June 4, 2024Assignee: Google LLCInventors: Houle Gan, Richard Stuart Roy, Yujeong Shim, William F. Edwards, Jr., Chenhao Nan
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Patent number: 11990461Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.Type: GrantFiled: October 20, 2022Date of Patent: May 21, 2024Assignee: Google LLCInventors: Nam Hoon Kim, Woon-Seong Kwon, Teckgyu Kang, Yujeong Shim
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Publication number: 20240036278Abstract: The technology generally relates to high bandwidth memory (HBM) and optical connectivity stacking. Disclosed systems and methods herein allow for 3D-stacking of HBM dies that are interconnected with an optical interface in a manner that allows for compact, high-performance computing. An optical chiplet can be configured to be placed onto a stack of HBM dies, with a cooling die that is positioned between the HBM dies and the optical chiplet. The optical chiplet may be configured to connect the HBM optics module package to one or more other components of the package via to one or more optical fibers.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Horia Alexandru Toma, Zuowei Shen, Yujeong Shim, Teckgyu Kang, Jaesik Lee, Georgios Konstadinidis, Sukalpa Biswas, Hong Liu, Biao He
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Publication number: 20230411297Abstract: A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.Type: ApplicationFiled: June 15, 2022Publication date: December 21, 2023Inventors: Georgios Konstadinidis, Woon-Seong Kwon, Jaesik Lee, Teckgyu Kang, Jin Y. Kim, Sukalpa Biswas, Biao He, Yujeong Shim
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Publication number: 20230402430Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.Type: ApplicationFiled: August 29, 2023Publication date: December 14, 2023Inventors: Namhoon Kim, Woon-Seong Kwon, Houle Gan, Yujeong Shim, Mikhail Popovich, Teckgyu Kang
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Patent number: 11830855Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.Type: GrantFiled: February 8, 2022Date of Patent: November 28, 2023Assignee: Google LLCInventors: Namhoon Kim, Woon-Seong Kwon, Houle Gan, Yujeong Shim, Mikhail Popovich, Teckgyu Kang
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Publication number: 20230343768Abstract: The technology generally relates to disaggregating memory from an application specific integrated circuit (“ASIC”) package. For example, a high-bandwidth memory (“HBM”) optics module package may be connected to an ASIC package via one or more optical links. The HBM optics module package may include HBM dies(s), HBM chiplet(s) and an optical chiplet. The optical chiplet may be configured to connect the HBM optics module to one or more optical fibers that form an optical link with one or more other components of the ASIC package. By including an optical chiplet in the HBM optics module package, the HBM optics module package may be disaggregated from an ASIC package.Type: ApplicationFiled: November 22, 2022Publication date: October 26, 2023Inventors: Horia Alexandru Toma, Zuowei Shen, Hong Liu, Yujeong Shim, Biao He, Jaesik Lee, Georgios Konstadinidis, Teckgyu Kang, Igor Arsovski, Sukalpa Biswas
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Publication number: 20230335928Abstract: An assembly includes a printed circuit board (“PCB”). An aperture extends through the PCB. The assembly also includes an array of pins and a processor package. The array of pins extends around a perimeter of the aperture, and the processor package extends over the aperture. The processor package is pressed against the array of pins by a compressive force couple.Type: ApplicationFiled: April 18, 2022Publication date: October 19, 2023Inventors: William F. Edwards, JR., Xu Zuo, Ryohei Urata, Melanie Beauchemin, Woon-Seong Kwon, Shinnosuke Yamamoto, Houle Gan, Yujeong Shim
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Publication number: 20230335541Abstract: A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contact pads that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board.Type: ApplicationFiled: April 13, 2022Publication date: October 19, 2023Inventors: Houle Gan, Richard Stuart Roy, Yujeong Shim, William F. Edwards, JR., Chenhao Nan
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Publication number: 20230042856Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.Type: ApplicationFiled: October 20, 2022Publication date: February 9, 2023Inventors: Nam Hoon Kim, Woon-Seong Kwon, Teckgyu Kang, Yujeong Shim
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Patent number: 11488944Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.Type: GrantFiled: January 25, 2021Date of Patent: November 1, 2022Assignee: Google LLCInventors: Namhoon Kim, Woon-Seong Kwon, Teckgyu Kang, Yujeong Shim
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Publication number: 20220238504Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.Type: ApplicationFiled: January 25, 2021Publication date: July 28, 2022Applicant: Google LLCInventors: Namhoon Kim, Woon-Seong Kwon, Teckgyu Kang, Yujeong Shim
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Publication number: 20220157787Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.Type: ApplicationFiled: February 8, 2022Publication date: May 19, 2022Inventors: Namhoon Kim, Woon-Seong Kwon, Houle Gan, Yujeong Shim, Mikhail Popovich, Teckgyu Kang
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Patent number: 11276668Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.Type: GrantFiled: February 12, 2020Date of Patent: March 15, 2022Assignee: Google LLCInventors: Nam Hoon Kim, Woon Seong Kwon, Houle Gan, Yujeong Shim, Mikhail Popovich, Teckgyu Kang
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Publication number: 20210249384Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.Type: ApplicationFiled: February 12, 2020Publication date: August 12, 2021Inventors: Nam Hoon Kim, Woon Seong Kwon, Houle Gan, Yujeong Shim, Mikhail Popovich, Teckgyu Kang
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Patent number: 9748934Abstract: Systems and methods for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. A power distribution network may supply power to components of an integrated circuit, and data driver circuitry may draw first current to drive a serial data signal generated from a parallel data signal. Compensation circuitry may receive the parallel data signal and draw second current at times when the compensation circuitry determines data driver circuitry is not drawing the first current based on the parallel data signal, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device.Type: GrantFiled: February 6, 2015Date of Patent: August 29, 2017Assignee: Altera CorporationInventors: Kyung Suk Oh, Yujeong Shim, Yanjing Ke, Tim Tri Hoang, Hae-Chang Lee
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Patent number: 8836384Abstract: Systems and methods are provided for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. In one example, a power distribution network may supply power to components of an integrated circuit and data driver circuitry may draw first current to drive a data signal. Compensation circuitry may draw second current at times when the data driver circuitry is not drawing the first current, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device (e.g., the power distribution network).Type: GrantFiled: August 2, 2013Date of Patent: September 16, 2014Assignee: Altera CorporationInventors: Kyung Suk Oh, Yujeong Shim, Tim Tri Hoang, Weiqi Ding, Sunitha Chandra
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Patent number: 7964944Abstract: The present invention is to implement a SOP of a mobile RFID interrogator. The substrate has external connection terminal patterns on a first surface of a substrate and circuit wiring patterns on a second surface of the substrate. a high frequency front-end part, a power amplifier IC, an analog-digital signal processing chip and the like are mounted on the second surface. The high frequency front-end part is to transmit and receive a RFID signal. The power amplifier IC is to output an amplified high frequency transmission signal to the high frequency front-end part. The analog-digital signal processing chip is to output a high frequency transmission signal to the power amplifier IC and process the RFID signal received through the high frequency front-end part, a mold resin is to cover the second surface and components mounted on the second surface for electrical insulation from outside and physical protection from outside.Type: GrantFiled: April 30, 2007Date of Patent: June 21, 2011Assignee: Korea Advanced Institute of Science and TechnologyInventors: Joungho Kim, Yujeong Shim
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Publication number: 20070285211Abstract: The present invention is to implement a SOP of a mobile RFID interrogator. The substrate has external connection terminal patterns on a first surface of a substrate and circuit wiring patterns on a second surface of the substrate. a high frequency front-end part, a power amplifier IC, an analog-digital signal processing chip and the like are mounted on the second surface. The high frequency front-end part is to transmit and receive a RFID signal. The power amplifier IC is to output an amplified high frequency transmission signal to the high frequency front-end part. The analog-digital signal processing chip is to output a high frequency transmission signal to the power amplifier IC and process the RFID signal received through the high frequency front-end part, a mold resin is to cover the second surface and components mounted on the second surface for electrical insulation from outside and physical protection from outside.Type: ApplicationFiled: April 30, 2007Publication date: December 13, 2007Inventors: Joungho Kim, Yujeong Shim