Patents by Inventor Yuji Amano
Yuji Amano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962480Abstract: An information management method collects log information of one or more home electrical apparatuses corresponding to service providers. Display screen data is generated which indicates a status of the log information. The display screen data includes groups of information which each contain information on an apparatus, a service provider corresponding to the apparatus, and log information output from the apparatus. Provision of the log information of each group is individually selectable. The display screen data is provided via a network to a display terminal that performs access to a server device. Information is received from the display terminal, which indicates that selection on whether or not provision of the log information is performed. Provision of the log information is not performed on the selected group when a determination is made that refusal of provision of the log information on the selected group is performed.Type: GrantFiled: March 13, 2023Date of Patent: April 16, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Hideki Matsushima, Motoji Ohmori, Natsume Matsuzaki, Yuichi Futa, Toshihisa Nakano, Manabu Maeda, Yuji Unagami, Hiroshi Amano, Kotaro Hakoda
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Patent number: 10278898Abstract: Disclosed is a method for shortening the drying time for drying an encapsulated material including a coating material containing water without causing deformation of the coating when drying. The method employs a fluidized bed dryer for drying coating materials that contain water and that form a coating when the water evaporates. A first drying step involves floating and fluidizing the encapsulated material and limiting a theorisable evaporating water content ?W so that dimples or deformation do not occur in the coating of the encapsulated granular material while measuring a water content or temperature of gas exhausted from the fluidized bed dryer; and a second drying step, performed after the measure water content is reduced below a prescribed amount or the measured temperature has increased, of blowing in gas to the fluidized bed dryer so that the theorisable evaporating water content ?W rises above that during the first drying step.Type: GrantFiled: June 26, 2014Date of Patent: May 7, 2019Assignee: R.P. Scherer Technologies, LLCInventors: Naoji Sawaguchi, Yuji Amano, Yuichiro Sakurai
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Publication number: 20170151130Abstract: Disclosed is a method for shortening the drying time for drying an encapsulated material including a coating material containing water without causing deformation of the coating when drying. The method employs a fluidized bed dryer for drying coating materials that contain water and that form a coating when the water evaporates. A first drying step involves floating and fluidizing the encapsulated material and limiting a theorisable evaporating water content ?W so that dimples or deformation do not occur in the coating of the encapsulated granular material while measuring a water content or temperature of gas exhausted from the fluidized bed dryer; and a second drying step, performed after the measure water content is reduced below a prescribed amount or the measured temperature has increased, of blowing in gas to the fluidized bed dryer so that the theorisable evaporating water content ?W rises above that during the first drying step.Type: ApplicationFiled: June 26, 2014Publication date: June 1, 2017Applicant: R.P. Scherer Technologies, LLCInventors: Naoji Sawaguchi, Yuji Amano, Yuichiro Sakurai
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Patent number: 7113161Abstract: An influence of a switching noise caused by a horizontal shift clock to an oscillation frequency of a voltage controlled oscillator should be eliminated, to prevent an image shift in a PAL skip period. For this purpose, an odd number line horizontal shift clock from an odd number line horizontal shift clock generator and an even number line horizontal shift clock from an even number line horizontal shift clock generator are switched by a horizontal shift clock switching circuit, to be input to a color LCD panel. The horizontal shift clock switching circuit selects and outputs either the odd number line horizontal shift clock or the even number line horizontal shift clock according to a line identifying signal, in a normal period. By contrast, in a PAL skip period a selecting state of the shift clock is inverted immediately upon start of a PAL skip period, from a selecting state right before the start of the skip period, and the selecting state is again inverted in half a cycle of a horizontal scanning period.Type: GrantFiled: November 10, 2003Date of Patent: September 26, 2006Assignee: Matsushita Electric Industiral Co., Ltd.Inventors: Yoshio Nirasawa, Yuji Amano, Norihide Kinugasa
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Patent number: 7064945Abstract: An output circuit may include a power supply terminal, a ground terminal, and an output terminal connected to a capacitive load. Depending on the state of a load control input signal, the output circuit performs selectively a charging-current supplying operation of supplying a charging-current from the power supply terminal to the capacitive load and a discharging-current withdrawing operation of withdrawing a discharging-current from the capacitive load to the ground terminal. An overcharging-current prevention switch is provided to detect a short circuit between the output terminal and the ground terminal so as to stop or suppress the charging-current supplying operation. An overdischarging-current prevention switch is provided to detect a short circuit between the output terminal and the power supply terminal so as to stop or suppress the discharging-current withdrawing operation.Type: GrantFiled: December 8, 2003Date of Patent: June 20, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuji Amano, Yoshio Nirasawa, Hideo Hamaguchi
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Publication number: 20040169980Abstract: An overcurrent is prevented from flowing in an output circuit when a short circuit occurs between an output terminal and a power supply terminal or a ground terminal. For this purpose, provided is an output circuit comprising a power supply terminal, a ground terminal, and an output terminal connected to a capacitive load. Depending on the state of a load control input signal, the output circuit performs selectively a charging-current supplying operation of supplying a charging-current from the power supply terminal to the capacitive load and a discharging-current withdrawing operation of withdrawing a discharging-current from the capacitive load to the ground terminal. Further, an overcharging-current prevention switch is provided for detecting a short circuit between the output terminal and the ground terminal so as to stop or suppress the charging-current supplying operation.Type: ApplicationFiled: December 8, 2003Publication date: September 2, 2004Inventors: Yuji Amano, Yoshio Nirasawa, Hideo Hamaguchi
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Publication number: 20040135759Abstract: An influence of a switching noise caused by a horizontal shift clock to an oscillation frequency of a voltage controlled oscillator should be eliminated, to prevent an image shift in a PAL skip period. For this purpose, an odd number line horizontal shift clock from an odd number line horizontal shift clock generator and an even number line horizontal shift clock from an even number line horizontal shift clock generator are switched by a horizontal shift clock switching circuit, to be input to a color LCD panel. The horizontal shift clock switching circuit selects and outputs either the odd number line horizontal shift clock or the even number line horizontal shift clock according to a line identifying signal, in a normal period. By contrast, in a PAL skip period a selecting state of the shift clock is inverted immediately upon start of a PAL skip period, from a selecting state right before the start of the skip period, and the selecting state is again inverted in half a cycle of a horizontal scanning period.Type: ApplicationFiled: November 10, 2003Publication date: July 15, 2004Inventors: Yoshio Nirasawa, Yuji Amano, Norihide Kinugasa
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Patent number: 6523701Abstract: A cassette for supporting substrates and an elongated rib therefor is described and represents a further improvement in the previously proposed elongated rib systems of the prior art and is designed particularly to preclude deflection and dampen vibrations of loaded substrates. The elongated ribs for the cassette project from side panels utilizing an elongated rib structure including three segments; namely, a base resin body, a bar-like intermediate resin body extending from the base resin body, and a terminal resin body disposed at the forward end of the intermediate resin body. Preferably, the elongated rib structure includes a linearreinforcing member inserted fromthe base resin body to the intermediate resin body or, alternatively, from the base resin body through the intermediate resin body to the terminal resin body.Type: GrantFiled: September 6, 2000Date of Patent: February 25, 2003Assignees: Yodogawa Kasei Kabushiki Kaisha, Sharp Kabushiki KaishaInventors: Toshio Yoshida, Yuji Amano, Taimi Oketani, Masayuki Tsuji, Isao Saraoka
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Patent number: 6390888Abstract: A grinder pressing device, wherein either the bottom part of a cylinder main body (10) of an air cylinder (1) in a vertical posture or a piston rod (11) is fixed to a fixed plate (2) and the other one is fixed to a movable plate (3) disposed under the fixed plate (2), either a guide table (G2) or a guide (G1) is mounted on the movable table (3) and the other one is mounted on the outer peripheral surface of the cylinder main body (20) and the guide plate (G2) is guided on the guide (G1) in a vertical direction under the rolling frictional condition through balls and, in the air cylinder (1), a coefficient of friction between the outer peripheral walls of a piston (12) and the piston rod (11) and the structural wall of the cylinder main body (10) is set lower by a metal seal so as to support the piston rod (11) by a ball bush movably in forward and backward directions over an extensive distance, a grinder (G) being mounted on the movable plate (3) and air pressures in upper and lower cylinder chambers (13 andType: GrantFiled: August 28, 2000Date of Patent: May 21, 2002Assignees: Nitta CorporationInventors: Yuji Amano, Yasuhiro Hayakawa
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Patent number: 5991533Abstract: A verification support system having the following characteristics: (1) Before actually making a CPU mounted circuit, virtually make a CPU mounted circuit model and an ICE model and perform verification of the CPU mounted circuit mode with logic simulation, by using the ICE model; (2) When an error is found in the verification of a program using logic simulation, the execution and verification of the steps up to one step before the error point is omitted and execution and verification are performed immediately from the error point, for the purpose of error correction; (3) A waveform obtained as a result of logic simulation and a partially enlarged waveform thereof are displayed on different display regions; (4) A display region for displaying a waveform obtained as a result of logic simulation every hour and a display region for saving a displayed waveform obtained when logic simulation is stopped, are provided separately; (5) When there are a plurality of target logic models, waveforms of logic simulation reType: GrantFiled: October 10, 1997Date of Patent: November 23, 1999Assignee: Yokogawa Electric CorporationInventors: Naoki Sano, Takeshi Yamamoto, Manabu Noriyasu, Satoru Natsui, Yuji Amano, Atsushi Ogasawara, Yuko Mizuta, Yoko Takihana
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Patent number: 5758123Abstract: A verification support system wherein before a CPU mounted circuit is actually made such circuit model and an ICE model are made virtually and verification of such circuit model is performed using logic simulation on the ICE model; and when an error is found execution and verification up to the error point are omitted and are performed immediately after the error point to correct the error. A waveform, obtained by logic simulation, and a partially enlarged waveform thereof are displayed on different display regions for each time period and a display region is provided for saving a displayed waveform obtained when logic simulation is stopped. In another aspect of the invention, before an actual system is made by PLC, such PLC model is verified, and a test program is carried out to obtain verification when a process model is detached from the PLC model, and a sequence program is carried out by using a general purpose simulator with a debugging function.Type: GrantFiled: April 11, 1995Date of Patent: May 26, 1998Assignee: Yokogawa Electric CorporationInventors: Naoki Sano, Takeshi Yamamoto, Manabu Noriyasu, Satoru Natsui, Yuji Amano, Atsushi Ogasawara, Yuko Mizuta, Yoko Takihana