Patents by Inventor Yuji Furumura

Yuji Furumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100060427
    Abstract: A base data management system is provided which can grasp specific data recorded in a plate-like or sheet-like object having high property values, such as a variety of cards, paper money, and securities, in real time, and can manage and track circulating paper money or the like. The base data management system 100 includes a base data reader 201 including reading means 203 that reads specific data or resonance frequency recorded in a base 10 with a magnetic field coupling and transmitting means 205 that transmits the specific frequency date read by the reading means and reader information.
    Type: Application
    Filed: November 26, 2007
    Publication date: March 11, 2010
    Inventors: Yuji Furumura, Naomi Mura, Shinji Nishihara, Katsuhiro Fujino, Katsuhiko Mishima, Susumu Kamihashi
  • Publication number: 20090289228
    Abstract: The present invention provides an RF powder having a characteristic to be used as a powder (powdery substance) which is composed of a large quantity of particles and has a collective form, wherein each of a large quantity of particles composing the powder is smaller in size as compared with a current IC tag chip and is used as a device having a function substantially equivalent to the IC tag chip, use form thereof is not individual device use but powder use, treatment is easy, a manufacturing cost is very low in respect of a unit cost of each particle, and a practical use is very high, and a method for manufacturing the same. An RF powder 11 is used in a powder form, wherein each particle 11a in the powder has an integrated circuit 13 formed on a substrate 12, an insulating layer 14 formed on the integrated circuit, and an antenna element 15 formed on the insulating layer.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Inventor: Yuji Furumura
  • Publication number: 20090289229
    Abstract: The present invention provides an RF powder-containing base including functional components, wherein forged cards, documents, bills, or the like are hard to be produced with respect to sheet-like subjects with high proprietary nature, such as various kinds of cards, bills, and securities, and each of a large number of particles can memorize information such as an identification number or the like. An RF powder-containing base 10 contains an RF powder (particles 11, 12, and 13), in which each particle of the RF powder provides an integrated circuit 15 formed on a substrate 14, an insulating layer 16 formed on the integrated circuit, and an antenna element 17 formed on the insulating layer, wherein each of the particles of the RF powder contained in the base has sensitivity to an electromagnetic waves having any of a plurality of different frequencies.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Inventor: Yuji Furumura
  • Publication number: 20090102025
    Abstract: A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the halogen being at least two members selected from the group consisting of F, I and Br. The ratio of at least one of I and Br is not more than 26% of the total amount of the halogen atoms as expressed in terms of the atomic compositional ratio to transfer the patterns onto the thin film. Such etching of a thin film avoids causing damage to the resist mask used. The resulting thin film carrying the transferred patterns is used as a mask for subjecting the underlying material to dry-etching.
    Type: Application
    Filed: April 7, 2006
    Publication date: April 23, 2009
    Inventors: Toshio Hayashi, Yasuhiro Morikawa, Michio Ishikawa, Yuji Furumura, Naomi Mura
  • Patent number: 5763005
    Abstract: For a multilayer insulating film of a semiconductor device, the distributed quantity of carbon or fluorine is maximized at the interface between insulating films. The concentration of carbon present at the interface is 1.times.10.sup.20 atoms/cm.sup.3 or more.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: June 9, 1998
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Masahiko Doki, Hidetoshi Nishio
  • Patent number: 5518937
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: May 21, 1996
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5506443
    Abstract: A multilayer insulating film of a semiconductor device, where the distributed quantity of carbon or fluorine is maximized at the interface between insulating films. The concentration of carbon present at the interface is 1.times.10.sup.20 atoms/cm.sup.3 or more.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: April 9, 1996
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Masahiko Doki, Hidetoshi Nishio
  • Patent number: 5314724
    Abstract: A process for the formation of a silicon oxide film, comprising the steps of exciting a gas comprising an organosilane or organosiloxane gas and a gas containing H and OH above a substrate in a reaction chamber to react them with each other in a gaseous phase or on the substrate, thereby depositing a thin film of an organic-group-containing silanol, silanol polymer, or siloxane-bonded polymer on the substrate, and removing the organic groups from the thin film to form a silicon oxide film. Preferably, the formation of a film is conducted while repeating the step of deposition and the step of removing the organic groups through a plasma treatment within an identical chamber, and the film is further heat-treated at a temperature of 450.degree. C. or below. Thus, a good insulating film having a flatness comparable to that of an SOG film can be obtained.
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: May 24, 1994
    Assignees: Fujitsu Limited, Fujitsu VlSI Limited
    Inventors: Atuhiro Tsukune, Yuji Furumura, Hatanaka Masanobu
  • Patent number: 5298458
    Abstract: A tungsten film is deposited on a substrate by a CVD process using a source gas comprising WF.sub.6, a silane group compound such as SiH.sub.4, Si.sub.2 H.sub.6, Si.sub.3 H.sub.8 or Si.sub.4 H.sub.10, and hydrogen fluoride or fluorine, at a lower temperature than in the prior art. The resultant tungsten film has low sheet resistance and good step coverage. The tungsten film may be selectively deposited.
    Type: Grant
    Filed: October 28, 1992
    Date of Patent: March 29, 1994
    Assignee: Fujitsu Limited
    Inventors: Fumitake Mieno, Yuji Furumura, Toshihiko Ono
  • Patent number: 5270224
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: January 17, 1992
    Date of Patent: December 14, 1993
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5233163
    Abstract: A heating apparatus for use in heating a substrate comprises an electric heater and a power supply part. The electric heater is made up of an approximately columnar body which is made of graphite, and this columnar body has a top with a flat surface part on which the substrate is placed and a pair of legs which extend downwardly from the flat surface part. The legs are defined by an opening in the columnar body. The power supplying part is coupled to the electric heater and supplies a voltage across the legs of the columnar body so that a current flows from one leg to the other, thereby generating heat at the flat surface part to heat the substrate.
    Type: Grant
    Filed: July 3, 1991
    Date of Patent: August 3, 1993
    Assignee: Fujitsu Limited
    Inventors: Fumitake Mieno, Yuji Furumura, Atsuhiro Tsukune, Hiroshi Miyata
  • Patent number: 5231057
    Abstract: A method for producing a semiconductor device includes the steps of forming a patterned wiring line on a first insulating layer, and depositing a second insulating layer on the patterned wiring line and the first insulating layer by a plasma-assisted CVD process in which a pulse-modulated plasma is generated and a gas containing hydrogen is used.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: July 27, 1993
    Assignee: Fujitsu Limited
    Inventors: Masahiko Doki, Junya Nakahira, Yuji Furumura
  • Patent number: 5111266
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: May 5, 1992
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5103285
    Abstract: A silicon carbide layer between a silicon substrate or layer and a metal layer because silicon carbide has many properties similar to those of silicon, has a very slow diffusion rate of a metal through the silicon carbide, or prevents a diffusion of a metal into the silicon, and can be deposited by CVD, which has an advantage of a good coverage over a step portion such as a contact window.
    Type: Grant
    Filed: December 19, 1988
    Date of Patent: April 7, 1992
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Takashi Eshita, Kikuo Itoh, Masahiko Doki
  • Patent number: 5082695
    Abstract: A method of fabricating an X-ray exposure mask including the steps of forming a .beta.-SiC membrane by chemcial vapor deposition and simultaneously doping the membrane with at least one of phosphorous, boron, nitrogen and oxygen.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: January 21, 1992
    Assignee: 501 Fujitsu Limited
    Inventors: Masao Yamada, Masafumi Nakaishi, Kenji Nakagawa, Yuji Furumura, Takashi Eshita, Fumitake Mieno
  • Patent number: 4906593
    Abstract: A method of producing a semiconductor device comprising the steps of: forming a window or contact hole in an insulating layer to expose a portion of a semiconductor substrate or a lower conductor line; forming semiconductor material (silicon) in the window; substituting the material with a metal (tungsten) by reaction of the semiconductor material with a metal compound (WF.sub.6 gas); and forming a conductor line over the metal within the window.
    Type: Grant
    Filed: March 4, 1988
    Date of Patent: March 6, 1990
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Shioya, Yuji Furumura, Yasushi Ohyama, Shin-ichi Inoue, Tsutomu Ogawa, Kiyoshi Watanabe, Hiroshi Goto
  • Patent number: 4876219
    Abstract: A method of forming a semiconductor thin layer on a silicon substrate comprising the steps of depositing a first amorphous layer of a compound semiconductor (e.g., GaAs) on the silicon substrate, and growing a first epitaxial layer of the compound semiconductor on the amorphous layer, characterized in that the method comprises the steps of: after the epitaxial growth step, depositing a second amorphous layer of the compound semiconductor on the first epitaxial layer, and growing a second epitaxial layer of the compound semiconductor on the second amorphous layer. The obtained GaAs/Si substrate has a reduced dislocation density.
    Type: Grant
    Filed: March 3, 1989
    Date of Patent: October 24, 1989
    Assignee: Fujitsu Limited
    Inventors: Takashi Eshita, Fumitake Mieno, Yuji Furumura, Takuya Watanabe
  • Patent number: 4855254
    Abstract: A single crystalline silicon carbide (.beta.-SiC) layer having a thickness greater than 1 .mu.m is grown on a silicon substrate by the following method of the present invention. The silicon substrate is provided in a reactor chamber, and the reactor chamber is evacuated and maintained at a reduced atmospheric pressure during the growing processes. While flowing a mixed gas containing acetylene into the reactor chamber, the substrate is heated up at a temperature range from 800.degree. to 1000.degree. C., preferable in a range from 810.degree. to 850.degree. C., whereby a buffer layer of carbonized silicon having a thickness of 60 to 100 .ANG. is grown on the substrate. Thereafter, the flowing gas is changed to a mixed gas containing hydrocarbon and chlorosilane, and the substrate temperature is raised to a temperature from 850.degree. to 950.degree. C. In this process, a single crystalline .beta.-SiC layer can be grown on the buffer layer, and a thickness of a few .mu.m for the grown .beta.
    Type: Grant
    Filed: December 13, 1988
    Date of Patent: August 8, 1989
    Assignee: Fujitsu Limited
    Inventors: Takashi Eshita, Fumitake Mieno, Yuji Furumura, Kikuo Itoh
  • Patent number: 4510177
    Abstract: A plurality of wafers on which semiconductor films having a uniform thickness and specific resistivity are obtained by a horizontal type low pressure vapor phase deposition system, i.e., a system using a horizontal reaction tube, in which wafers are aligned in parallel and transverse to a longitudinal axis of the tube. A main gas is introduced from a main inlet into the reaction tube and an auxiliary gas including an impurity gas is introduced from an auxiliary inlet into the reaction tube in such a manner that the impurity gas diffuses toward the main inlet along an inner wall of the reaction tube.
    Type: Grant
    Filed: August 4, 1982
    Date of Patent: April 9, 1985
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Takeshi Nishizawa
  • Patent number: 4509070
    Abstract: A metal-insulator-semiconductor (MIS) device comprising a MIS transistor and a MIS input element which are fabricated apart from each other on a semiconductor substrate. The MIS transistor is provided with source and drain regions as well as a channel region between the source and drain regions, a gate insulating layer on the channel region and a gate on the insulating layer. The MIS input element is provided with an input region of the same conductive type as the channel region, an insulating layer on the input region and an electrode on the insulating layer. The electrode and insulating layer of the input element are made of the same material in the same thickness as the gate and insulating layer of the MIS transistor, and the gate of the MIS transistor is exclusively electrically interconnected to the electrode of the MIS input element.
    Type: Grant
    Filed: December 18, 1980
    Date of Patent: April 2, 1985
    Assignee: Fujitsu Limited
    Inventor: Yuji Furumura