Abstract: A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory.

Abstract: A storage device is for restoring the data saved in a nonvolatile memory to a cache memory, even if there is not a read response from the nonvolatile memory. In a data saving operation, parity data of to-be-saved data is generated, and the to-be-saved data and the parity data having CRCs and AIDs added thereto are written into a flash memory. In a data restoring operation, if an operation to read data from the flash memory is not completed within a predetermined period of time, the data reading operation is suspended, and additional data is set. The to-be-saved data having a data error corrected with the parity data is then written into the cache memory.

Abstract: A backup method makes a backup of cache data to a nonvolatile memory by using a controller, the cache data being stored in the volatile memory. The backup method includes writing the cache data stored in the volatility memory in a selected area of the nonvolatile memory, generating party data by operating the parity operations between each of the predetermined parts of the cache data in the volatile memory, verifying whether an error found in the part of the cache data in the nonvolatile memory can be recovered by using the parity data, and rewriting the part of the cache data when the error found in the part of the cache data in the nonvolatile memory cannot be recovered by using the parity data in an area of the nonvolatile memory different from the selected area.

Abstract: A storage apparatus includes a backup processing unit that stores data stored in a first memory into a second memory as backup data upon occurrence of a power failure, a restore processing unit that upon recovery from the power failure restores the backup data backed up in the second memory to the first memory and erases the backup data, and an erasure processing termination unit that terminates the erasure processing upon a power failure occurring during erasure processing for erasing the backup data stored in the second memory, and a re-backup processing unit that re-backs up data in the first memory corresponding to the backup data erased from the second memory before the erasure processing is terminated by the erasure processing termination unit to a location in the second memory subsequent to a last location that contains the backup data which has not been erased.

Abstract: An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and transferring data of the data stream in synchronism with a first clock signal, and holding the received data until an input of a next data, an asynchronous memory for sequentially receiving the data held in the data holding circuit in synchronism with the first clock signal and for outputting the data in the order of inputting in synchronism with a second clock signal. The asynchronous interface circuit further includes a monitor for detecting an operating state of the asynchronous memory, and a selector for selecting one of the data output from the asynchronous memory and the data output from the data holding circuit on the basis of a detecting result of the monitor.

Abstract: A controlling apparatus for controlling a disk array unit includes a cache memory for caching data of the disk array unit; a nonvolatile memory for storing the data in the cache memory; and a control unit for detecting a defective location in the nonvolatile memory where the data is stored defectively and updating information indicating the defection location, for generating an error detection code of the updated information, for writing the generated information and the associated error detection code into an area of the nonvolatile memory different from any area where any information indicating any defective location previously detected and stored into the nonvolatile memory, and for controlling writing the data in the cache memory into a location of the nonvolatile memory designated by any selected one of the information stored in the nonvolatile memory.

Abstract: An information processing apparatus includes, a first storage unit, a second storage unit in which data stored in the first storage unit is backed up, and a memory controller that controls data backup operation. The memory controller divides a transfer source storage area into portions, and provides two transfer destination areas, each of the two transfer destination areas being divided into portions, backs up data in a direction from a beginning address of each divided area of the transfer source storage area to an end address thereof in one of the transfer destination areas provided for each divided area of the transfer source storage area, and backs up data in a direction from the end address of each divided area of the transfer source storage area to the beginning address thereof in the other transfer destination storage area.

Abstract: A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.

Abstract: A data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined time period, wherein: in the reading request re-issuing step, a flag is attached to the re-reading request, and thus, the re-reading request is differed from the first issued reading request.

Abstract: A data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined time period, wherein: in the reading request re-issuing step, a flag is attached to the re-reading request, and thus, the re-reading request is differed from the first issued reading request.

Abstract: A data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined time period, wherein: in the reading request re-issuing step, a flag is attached to the re-reading request, and thus, the re-reading request is differed from the first issued reading request.

Abstract: A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.

Abstract: Priorities are set in order of an internal register access packet, a response system packet, and a command system packet which are transmitted/received by a packet transmitting/receiving unit. In a transfer waiting state of the command system packet of the low priority to a certain transmission destination, in the case where the response system packet or internal register access packet of the high priority to another transmission destination is received from an external module, the packet transmitting/receiving unit withdraws the transfer waiting state and transmits the packet of the high priority.

Abstract: The present invention provides a shrink-wrapped package comprising at least one article shrink-wrapped with a polyester film containing an ethylene terephthalate unit, the shrink-wrapped package having a portion of sealing and cutting whose starting point has a movement distance of 10 &mgr;m or less.

Abstract: The present invention provides a shrink-wrapped package comprising at least one article shrink-wrapped with a polyester film containing an ethylene terephthalate unit, the shrink-wrapped package having a portion of sealing and cutting whose starting point has a movement distance of 10 &mgr;m or less.

Abstract: The present invention provides a heat shrinkable film comprising at least one layer of a thermoplastic resin and having a heat shrinkage in the main orientation direction of 10% or less after treatment in a hot water at 70° C. for 2 seconds, and 65% or more after treatment in hot water at 90° C. for 10 seconds, the heat shrinkable film preferably having a natural shrinkage in the main orientation direction of 2.5% or less after being allowed to stand at 40° C. for 7 days.

Abstract: Priorities are set in order of an internal register access packet, a response system packet, and a command system packet which are transmitted/received by a packet transmitting/receiving unit. In a transfer waiting state of the command system packet of the low priority to a certain transmission destination, in the case where the response system packet or internal register access packet of the high priority to another transmission destination is received from an external module, the packet transmitting/receiving unit withdraws the transfer waiting state and transmits the packet of the high priority.