Patents by Inventor Yuji Hara

Yuji Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090060390
    Abstract: An image processing apparatus has a plurality of serially connected image processing blocks for sequentially processing image data input thereto. After a first command for controlling the plurality of image processing blocks and image data to be processed by the plurality of image processing blocks are output to the leading image processing block, a second command indicating end of this output is output to the leading image processing block. When the second command is output from a final image processing block, the next first command and image data are output to the leading image processing block.
    Type: Application
    Filed: August 12, 2008
    Publication date: March 5, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yuji Hara, Hisashi Ishikawa
  • Publication number: 20090043062
    Abstract: To provide a powder coating composition which prevents blocking in powder coating and simultaneously achieves suitable appearance and flexibility of the coated film. A powder coating composition comprising a fluorinated copolymer (X) having a glass transition point of at least 50° C. and a number average molecular weight of from 10,000 to 22,000, and a curing agent (Y), wherein the fluorinated copolymer (X) is a copolymer obtained by polymerization of a monomer mixture comprising (A) from 45 to 55 mol % of chlorotrifluoroethylene and/or tetrafluoroethylene, (B) from 2 to 40 mol % of a vinyl ether which has a C4 or 5 alkyl group containing a tertiary carbon atom, (C) from 5 to 20 mol % of a vinyl ether having a crosslinkable functional group and (E) from 0 to 32 mol % of a vinyl ester which has a C3-5 alkyl group containing a tertiary or higher carbon atom, wherein the total content of the above (B) and (E) is from 30 to 50 mol %, and the curing agent (Y) is reactive with the crosslinkable functional group.
    Type: Application
    Filed: October 10, 2008
    Publication date: February 12, 2009
    Applicant: Asahi Glass Company, Limited
    Inventors: Sho MASUDA, Yuji Hara, Kouichi Sasaki
  • Publication number: 20090027404
    Abstract: An image processing apparatus comprises a plurality of processing blocks connected in series, and each respective processing block comprises a processor. In each respective processing block, the processor employs data input into that processing block to perform an image process upon the data. Also, each processing block performs a process upon the processor in response to a command input into the processing block. Each processing block causes an output corresponding to the command that is input after the data to wait until an output of the processor that employed the data input into the processing block prior to the command to perform the process is finished, such that the output of the processor that employed the data to perform the image processing and the output that corresponds to the command is outputted from the processing block in an order whereby the data and the command are input.
    Type: Application
    Filed: July 16, 2008
    Publication date: January 29, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yuji Hara, Hisashi Ishikawa
  • Patent number: 6891888
    Abstract: The image processing method and apparatus read photoelectrically an original image to obtain input image data and subject the input image data to image processing to obtain output image data. The method and apparatus perform first conversion for outputting an image file and second conversion for outputting a print as the image processing on the input image data obtained by a single image reading operation and output first image data for outputting the image file and second image data for outputting the print. The method and apparatus make it possible to output both of the photographic print and the image file, which have a good image quality, by a simple operation and with a high operation efficiency.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: May 10, 2005
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Jun Enomoto, Yuji Hara
  • Patent number: 6573170
    Abstract: A semiconductor integrated circuit device including a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 3, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Aoyagi, Atsushi Ogishima, Hirotaka Kobayashi, Yuji Hara
  • Publication number: 20010033370
    Abstract: The image processing method and apparatus read photoelectrically an original image to obtain input image data and subject the input image data to image processing to obtain output image data. The method and apparatus perform first conversion for outputting an image file and second conversion for outputting a print as the image processing on the input image data obtained by a single image reading operation and output first image data for outputting the image file and second image data for outputting the print. The method and apparatus make it possible to output both of the photographic print and the image file, which have a good image quality, by a simple operation and with a high operation efficiency.
    Type: Application
    Filed: March 23, 2001
    Publication date: October 25, 2001
    Inventors: Jun Enomoto, Yuji Hara
  • Publication number: 20010019180
    Abstract: A semiconductor integrated circuit device comprises a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 6, 2001
    Inventors: Takashi Aoyagi, Atushi Ogishima, Hirotaka Kobayashi, Yuji Hara
  • Publication number: 20010005624
    Abstract: A semiconductor integrated circuit device comprises a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Inventors: Takashi Aoyagi, Atsushi Ogishima, Hirotaka Kobayashi, Yuji Hara
  • Patent number: 5900884
    Abstract: A parametric curve generating device for developing a Bezier curve is provided. The device is capable of executing a high speed division operation with a limited magnitude of hardware scale. Adders perform calculations that are stored in registers. Convergence discrimination circuits discriminate whether data stored in the registers converge. Subsequent processing varies depending on the discrimination result. A stack memory is used to store data from the registers.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: May 4, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiaki Minami, Tatsuhiko Yamazaki, Hayao Ohzu, Yuji Hara
  • Patent number: 5872574
    Abstract: A minimum coordinate value at least in one direction of a parameter data group including a start point and an end point of a stroke is detected and outline coordinates are generated from the parameter data group by an outline coordinate generator and a minimum coordinate detector. An outline data generator stores range data indicative of a painting range into a predetermined address in an outline buffer on the basis of the outline coordinates and the minimum coordinate value or the maximum coordinate value. An address generator generates a drawing start address and an end address in a bit map memory in accordance with a value based on the minimum coordinate value and the predetermined address and with the range data. A painter paints by writing the same value into all data between the drawing start address and end address in the bit map memory, thereby generating a character pattern at a high speed by a buffer memory of a small capacity.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: February 16, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuji Hara, Tatsuhiko Yamazaki, Hayao Ohzu, Toshiaki Minami
  • Patent number: 5583381
    Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: December 10, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
  • Patent number: 5552639
    Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: September 3, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
  • Patent number: 5539257
    Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: July 23, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
  • Patent number: 5468998
    Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: November 21, 1995
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
  • Patent number: 5371411
    Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: December 6, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
  • Patent number: 5229642
    Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.
    Type: Grant
    Filed: May 21, 1991
    Date of Patent: July 20, 1993
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
  • Patent number: 5155701
    Abstract: An EPROM and a method of testing the former, in which a defective memory cell caused by defects in the insulating films between a substrate and a floating gate and between the floating gate and a control gate can be tested without writing any data in the individual memory cells by holding data lines to a low potential and word lines fed with a voltage.
    Type: Grant
    Filed: June 8, 1990
    Date of Patent: October 13, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Komori, Yuji Hara, Hideaki Takahashi, Minoru Fukuda, Satoshi Meguro
  • Patent number: 5023699
    Abstract: A resin molded type semiconductor device has a metallic ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the ring.
    Type: Grant
    Filed: October 10, 1989
    Date of Patent: June 11, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya
  • Patent number: 4625227
    Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.
    Type: Grant
    Filed: June 13, 1985
    Date of Patent: November 25, 1986
    Assignees: Hitachi, Ltd, Hitachi Microcomputer Engineering, Ltd.
    Inventors: Yuji Hara, Satoru Ito, Tatsuro Toya