Abstract: A redundant circuit for a SRAM device is provided. The redundant circuit includes: a pair of a first transistor and a second transistor, connected between a power source voltage and a power source terminal of each of the input/output memory units, wherein the pair of the first transistor and the second transistor are connected in parallel with each other, and the first transistor has a greater mutual conductance than the second transistor; and a redundancy control circuit configured to detect a voltage of the power source terminal of each of the input/output memory units when the first transistor is turned off and the second transistor is turned on. When the detected voltage of the power source terminal is decreased by a predetermined value or more from a predetermined reference voltage, the input/output memory unit is determined in a defective state, and the input/output memory unit in the defective state is redundantly replaced with a normal input/output memory unit.

Abstract: A redundant circuit for a SRAM device is provided. The redundant circuit includes: a pair of a first transistor and a second transistor, connected between a power source voltage and a power source terminal of each of the input/output memory units, wherein the pair of the first transistor and the second transistor are connected in parallel with each other, and the first transistor has a greater mutual conductance than the second transistor; and a redundancy control circuit configured to detect a voltage of the power source terminal of each of the input/output memory units when the first transistor is turned off and the second transistor is turned on. When the detected voltage of the power source terminal is decreased by a predetermined value or more from a predetermined reference voltage, the input/output memory unit is determined in a defective state, and the input/output memory unit in the defective state is redundantly replaced with a normal input/output memory unit.

Abstract: The power control circuit of the disclosure is configured for a logic circuit performing a predetermined logic calculation on a plurality of input signals from a memory part and outputting a plurality of output signals after logic calculation. The power control circuit includes a switch part that switches between whether to supply a power voltage to the logic circuit or not; a plurality of detector circuits that respectively detect change of signal level of the input signals, wherein when the change of signal level is detected, detect signals are output respectively; and a control circuit that controls the switch part to supply power voltage to the logic circuit based on at least one detect signal from the detector circuits, wherein on the other hand, when the detect signal is not output from the detector circuits, controls the switch part not to supply power voltage to the logic circuit.

Abstract: A refresh control circuit of a volatile semiconductor memory device is provided, where the volatile semiconductor memory device includes a plurality of memory cells respectively having a select transistor and a memory element, and the refresh control circuit of the volatile semiconductor memory device includes: a first comparison part, which compares a memory voltage of the memory cell of the volatile semiconductor memory device that is different to a general-memorizing memory cell with a specified threshold voltage, and outputs a comparison result signal, and stops self refresh of the memory cell until the memory voltage is decreased to be smaller than the specified threshold voltage. The memory cell is formed in a region adjacent to an array of the general-memorizing memory cell.

Abstract: The semiconductor memory device of the invention includes 2 TFT MOS transistors, 2 bulk MOS transistors, a first and second access MOS transistors and a first and second capacitor. The TFT and bulk MOS transistors form a latch for retaining a data that is inverted between a first and second node. The first bulk access MOS transistor switches the first node to connect to a first bit line according to a voltage of a word line. The second bulk access MOS transistor, switches the second node to connect to a second bit line according to the voltage of the word line. The first capacitor is disposed between the first node and a power supply voltage. The second capacitor is disposed between the second node and the power supply voltage. The bulk MOS transistors and the access MOS transistors are formed by a recess gate type MOS transistor.

Abstract: A vehicle wheel having a rim and a disk. A disk flange of the disk may have a non-contact portion non-contacting a radially inner surface of the rim, at a radially outer extension of a width center line of a spoke. As a result, the rigidity of a portion of the disk in the circumferential direction of the wheel where the spoke is provided may be decreased compared with a wheel (conventional) where such non-contact portion is not provided. A difference in rigidity of the disk in the circumferential direction of the wheel between a portion where the vent window is provided and a portion where the spoke is provided may be smaller than that in the case of the conventional wheel, whereby a durability of the wheel and a run-out accuracy of the wheel may be improved.

Abstract: The technology provides vehicle wheels that can include a hub coupling portion and a spoke. The spoke can have a waved portion at a portion of the spoke in the radial direction of the wheel and can be decreased in section modulus at a cross section of the portion of the spoke taken along a plane perpendicular to the radial direction of the wheel. The waved portion can be formed by displacing the spoke bottom wall and/or the spoke reinforcing walls in the axial direction of the wheel.

Abstract: A vehicle wheel disk includes a plurality of spoke portions extending radially outwardly from a hub coupling portion with vent windows between the spokes. Each spoke includes a bottom wall and axially extending side walls, with a radially outer disk portion connecting the radially outer ends of the spokes. A connecting wall connects a pair of spoke side portions on opposite sides of the vent window in the circumferential direction of the wheel. The spoke bottom wall includes an axially extending inclined portion and a radially extending main portion. A spoke strengthening wall extends circumferentially from the axial end of the spoke side wall. The connecting wall includes a vent window surrounding portion, a vent window surrounding curved portion, and a crest wall portion of a radially inwardly protruding protrusion.

Abstract: The technology provides vehicle wheel disks where a spoke portion can have a spoke bottom wall and a spoke side portion. The spoke side portion can include a spoke side wall rising from the spoke bottom wall in an axial direction of the wheel and a spoke reinforcing wall connected from an axially end portion of the spoke side wall and curved from the axial direction of the wheel toward a circumferential direction of the wheel and extending in the circumferential direction of the wheel. A pair of spoke side portions can be located on opposite sides of the vent window in the circumferential direction of the wheel have radially inner end portions which are connected to each other via a connecting wall. The connecting wall can be flat or substantially flat in the circumferential direction of the wheel.

Abstract: A vehicle wheel having a rim and a disk. A disk flange of the disk may have a non-contact portion non-contacting a radially inner surface of the rim, at a radially outer extension of a width center line of a spoke. As a result, the rigidity of a portion of the disk in the circumferential direction of the wheel where the spoke is provided may be decreased compared with a wheel (conventional) where such non-contact portion is not provided. A difference in rigidity of the disk in the circumferential direction of the wheel between a portion where the vent window is provided and a portion where the spoke is provided may be smaller than that in the case of the conventional wheel, whereby a durability of the wheel and a run-out accuracy of the wheel may be improved.

Abstract: The technology provides vehicle wheels that can include a hub coupling portion and a spoke portion. The spoke portion can have a waved portion at a portion of the spoke portion in the radial direction of the wheel and can be decreased in section modulus at a cross section of the portion of the spoke portion taken along a plane perpendicular to the radial direction of the wheel. The waved portion can be formed by displacing the spoke bottom wall and/or the spoke reinforcing walls in the axial direction of the wheel.

Abstract: The technology provides vehicle wheel disks where a spoke portion can have a spoke bottom wall and a spoke side portion. The spoke side portion can include a spoke side wall rising from the spoke bottom wall in an axial direction of the wheel and a spoke reinforcing wall connected from an axially end portion of the spoke side wall and curved from the axial direction of the wheel toward a circumferential direction of the wheel and extending in the circumferential direction of the wheel. A pair of spoke side portions can be located on opposite sides of the vent window in the circumferential direction of the wheel have radially inner end portions which are connected to each other via a connecting wall. The connecting wall can be flat or substantially flat in the circumferential direction of the wheel.

Abstract: A vehicle wheel disk comprising: a hub coupling portion surrounding a hub hole; a plurality of spoke portions each extending outwardly in a radial direction of a wheel from the hub coupling portion and having a spoke bottom wall and a spoke side portion; a vent window located between adjacent spoke portions of the plurality of spoke portions; a disk radially outer portion located at a radially outer end portion of the wheel and connecting radially outer end portions of the plurality of spoke portions in a circumferential direction of the wheel; and a connecting wall located radially inside the disk radially outer portion and connecting a pair of spoke side portions located on opposite sides of the vent window in the circumferential direction of the wheel; wherein the spoke bottom wall includes a bottom wall inclined portion extending outwardly in an axial direction of the wheel from the hub coupling portion, and a bottom wall main portion extending outwardly in the radial direction of the wheel from the botto

Abstract: During operation, a control signal attains H level, a conventional type first reference voltage generation circuit is activated, and the first reference voltage generation circuit generates a reference voltage. During stand-by, the control signal attains L level, and the first reference voltage generation circuit is inactivated, whereby a through current does not flow through the first reference voltage generation circuit. Then, during stand-by, an internal voltage generation circuit is supplied with the reference voltage generated by a second reference voltage generation circuit including a resistance division circuit constituted of first to third resistors each having a high resistance value of T (tera) ? order, in which a through current is extremely small.

Abstract: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.

Abstract: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.

Abstract: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.

Abstract: During operation, a control signal attains H level, a conventional type first reference voltage generation circuit is activated, and the first reference voltage generation circuit generates a reference voltage. During stand-by, the control signal attains L level, and the first reference voltage generation circuit is inactivated, whereby a through current does not flow through the first reference voltage generation circuit. Then, during stand-by, an internal voltage generation circuit is supplied with the reference voltage generated by a second reference voltage generation circuit including a resistance division circuit constituted of first to third resistors each having a high resistance value of T (tera) ? order, in which a through current is extremely small.

Abstract: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.

Abstract: A memory cell is provided with an N-channel MOS transistor as a transfer gate, a capacitor for accumulating charges corresponding to stored information, and a charge compensating circuit. Charge compensating circuit is a bi-stable circuit formed of two stages of inverters and latches a logic level of a node. Load resistors of inverters are constituted of P-channel thin film transistors made of polycrystalline polysilicon which can be formed on upper layers of N-channel MOS transistors as bulk transistors. As a result, a semiconductor memory device can realize a higher packing density and a larger capacity close to those of a DRAM without requiring refresh operations.