Abstract: A clock signal is frequency divide to generate a plurality of signals CK, CK′ having different periods, and a plurality of the control signals C, TZS are generated from them. One of the control signals C, TZS is selected as control signal TZ1, depending on the comparison section T1-T4, so as to change the period of the control signal for each comparison section. The reference voltage and the input voltage are compared according to the control signal TZ1. The period of the control signal is made shorter at the comparison sections other than the section T2 which requires a longer comparison time for the stabilization of the reference voltage, due to the large difference of the former reference voltage and the present reference voltage.

Abstract: A method of controlling an analog-to-digital (A/D) converter for converting an input voltage into digital data. The conversion process includes charging a capacitor with the input voltage to be converted into a digital data, and disconnecting the input voltage from the capacitor. A reference voltage, generated according to digital data, is furnished by a control circuit to a digital-to-analog (D/A) converting unit. The reference voltage is applied to the capacitor by turning on a switch connected between the D/A converting unit and the capacitor. New digital data to be furnished by the control circuit is determined according to a charged voltage on the capacitor. The D/A converting unit causes the reference voltage to be delivered to the capacitor to change to a new value according to the new digital data from the control circuit.