Abstract: A light-emitting component includes: a substrate; plural light-emitting elements that are disposed on the substrate and that emit light in a direction intersecting with a surface of the substrate; and plural thyristors that are stacked on the plural light-emitting elements and that are turned ON to drive the corresponding light-emitting elements so that the light-emitting elements emit light or an amount of light emitted from the light-emitting elements is increased. Each of the plural light-emitting elements includes a current confinement region which is oxidized via a hole provided in a multilayer structure. The multilayer structure is constituted by a corresponding light-emitting element and a corresponding thyristor.

Abstract: The present invention provides a matching result display device, a matching result display method, a program, and a recording medium, which allow, at the time of displaying feature points of objects determined as matching on the basis of matching result information provided by a matching system, visual check of the displayed feature points to be performed easily.

Abstract: An arithmetic processor performs arithmetic processing, and a synchronization processor, including first registers, performs synchronization processing that includes a plurality of processing stages to be processed stepwise. The arithmetic processor sends, to the synchronization processor, setting information to be used in a predetermined processing stage of the synchronization processing, and instruct the synchronization processor to execute the predetermined processing stage for the arithmetic processing. Each of the first registers includes a setting information management area to manage the setting information received from the arithmetic processor, and a destination status area to store a usage state of each of destination registers which are used in a next processing stage following the predetermined processing stage.

Abstract: A memory access controller includes a request issuing circuit to issue a user request in response to a memory request, issue a refresh request at first issuing intervals, and issue a scrubbing request at second issuing intervals; and a command issuing circuit to issue a first active to a memory via a row command bus and issue M reads to the memory via a column command bus after the first active is issued, when memory access for the user request is to be executed, issue refresh to the memory via the row command bus when the memory access for the refresh request is executed, and issue a second active to the memory via the row command bus and issues N (>M) reads to the memory via the column command bus after the second active is issued, when the memory access for the scrubbing request is to be executed.

Abstract: A memory is accessed based on memory access requests that has different data read sizes. A memory access method includes outputting each of read commands corresponding to the plurality of memory access requests to a memory at a timing that avoids conflict of read data output from the memory; generating an output start timing of the data read from the memory to an outside; retaining the data read from the memory in each of buffers, and causing any of the plurality of buffers to output data based on the output start timing; and delaying, in a case of receiving a subsequent memory access request during execution of memory access corresponding to a preceding memory access request, the output start timing of data from the buffer corresponding to the subsequent memory access request from the output start timing of data from the buffer corresponding to the preceding memory access request.

Abstract: A memory access controller includes a request issuing circuit to issue a user request in response to a memory request, issue a refresh request at first issuing intervals, and issue a scrubbing request at second issuing intervals; and a command issuing circuit to issue a first active to a memory via a row command bus and issue M reads to the memory via a column command bus after the first active is issued, when memory access for the user request is to be executed, issue refresh to the memory via the row command bus when the memory access for the refresh request is executed, and issue a second active to the memory via the row command bus and issues N (>M) reads to the memory via the column command bus after the second active is issued, when the memory access for the scrubbing request is to be executed.

Abstract: A memory is accessed based on memory access requests that has different data read sizes. A memory access method includes outputting each of read commands corresponding to the plurality of memory access requests to a memory at a timing that avoids conflict of read data output from the memory; generating an output start timing of the data read from the memory to an outside; retaining the data read from the memory in each of buffers, and causing any of the plurality of buffers to output data based on the output start timing; and delaying, in a case of receiving a subsequent memory access request during execution of memory access corresponding to a preceding memory access request, the output start timing of data from the buffer corresponding to the subsequent memory access request from the output start timing of data from the buffer corresponding to the preceding memory access request.

Abstract: An arithmetic processor includes a memory access controller configured to control access of a memory based on a memory access request. The memory access controller includes a shift register configured to shift a resource number and a memory access request from a first stage to a subsequent stage of the first stage at a timing according to the operation mode, the first stage is received a resource number and a memory access request. The memory access controller includes a plurality of memory access transmitting circuits configured to receive the resource number and the memory access request held by the plurality of stage. Each of the plurality of access transmitting circuits provided corresponding to the plurality of resource number, and output, to the memory, an access command corresponding to the memory access request when the received resource number matches a resource number of a memory access transmitting circuit.

Abstract: A circuit board being able to easily ensure flatness of solder placed on a substrate for bonding an electronic component and improve bonding reliability of the electronic component by the solder, includes: a substrate having a plurality of layers made of a conductive material; a land provided on a first layer arranged on one side of the substrate, to which the electronic component is soldered; a heat sink provided on a different layer arranged on the substrate; a via hole provided on the substrate from a part of the land over to a part of the heat sink and electrically connected to the land and the heat sink; and an insulating resist disposed on the land and surrounding the entire circumference of the via hole.

Abstract: The present invention includes methods for treating and/or preventing a viral or virally-induced tissue dysfunction or failure in a patient comprising administering an inhibitor of SARS-CoV-2 binding to L-SIGN in an amount effective to treat the viral or virally-induced tissue dysfunction or failure of cells do not express ACE2.

Abstract: An arithmetic processor includes a memory access controller configured to control access of a memory based on a memory access request. The memory access controller includes a shift register configured to shift a resource number and a memory access request from a first stage to a subsequent stage of the first stage at a timing according to the operation mode, the first stage is received a resource number and a memory access request. The memory access controller includes a plurality of memory access transmitting circuits configured to receive the resource number and the memory access request held by the plurality of stage. Each of the plurality of access transmitting circuits provided corresponding to the plurality of resource number, and output, to the memory, an access command corresponding to the memory access request when the received resource number matches a resource number of a memory access transmitting circuit.

Abstract: A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

Abstract: The disclosure provides a pull and a manufacturing method of the pull, which can mount an electronic component inside a handle part without damaging the electronic component and have favorable electronic functions. The pull of the disclosure is to be mounted on a slider for a slide fastener, and includes a ring part, an insertion part, the handle part, and the electronic component. The ring part is to be mounted on the slider. The insertion part is connected to the ring part for receiving an injection material. The handle part is formed sequentially on the insertion part by the injection material. The electronic component is mounted inside the handle part in a process in which the handle part is formed sequentially on the insertion part by the injection material.

Abstract: An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.

Abstract: Provided is a joint device which can be connected by quick and simple operation while being subjected to high-pressure high-flow-rate pressurized operating oil. The present invention comprises: a closed chamber 27 provided in a hydraulic circuit on which pressurized fluid acts, the pressurized fluid circuit having an upstream side and a downstream side, which are closed by an upstream-side stop valve 211 and a downstream-side stop valve 212; a male joint 30 provided at a position in communication with the closed chamber 27; and a female joint 40 connectable to the male joint 30 and provided in an emergency hydraulic circuit connected to the hydraulic circuit. The present invention is configured so that the female joint 40 is connected to the male joint 30 while the closed chamber 27 is closed by the upstream-side stop valve 211 and the downstream-side stop valve 212.

Abstract: In a parallel computer system having multiple information processing apparatuses, a first information processing apparatus includes circuitry configured to wait for calculation target data from each of one or more other information processing apparatuses being included in the plurality of information processing apparatus; carry out an average calculation that calculates an average value of a plurality of calculation target data including the waited calculation target data; and transmit the calculated average value to a second information processing apparatus being one of the plurality of information processing apparatuses and being different from the other information processing apparatuses. This configuration makes it possible to achieve highly-precise collective average calculation without requiring bit expansion.

Abstract: An arithmetic processor performs arithmetic processing, and a synchronization processor, including first registers, performs synchronization processing that includes a plurality of processing stages to be processed stepwise. The arithmetic processor sends, to the synchronization processor, setting information to be used in a predetermined processing stage of the synchronization processing, and instruct the synchronization processor to execute the predetermined processing stage for the arithmetic processing. Each of the first registers includes a setting information management area to manage the setting information received from the arithmetic processor, and a destination status area to store a usage state of each of destination registers which are used in a next processing stage following the predetermined processing stage.

Abstract: The present invention includes a method of treating a bone disease caused by a intracellular protein trafficking defect comprising: identifying a subject having the bone disease caused by the intracellular protein trafficking defect in a membrane bound transcription factor peptidase, site 1 (MBTPS1) gene; and providing the subject with an effective amount of a composition that bypasses or corrects a defect in MBTPS1 gene expression, gene splicing, or corrects protein trafficking defects in the endoplasmic reticulum and to the lysosome.

Abstract: A display device includes a display panel divided into a display region and a non-display region, the display panel including a panel pad part on the non-display region, a driving circuit substrate including a driving pad part, the driving circuit substrate to provide a driving signal to the display panel, a panel connecting substrate including a first connecting pad part and a second pad part, the panel connecting substrate to electrically connect the display panel and the driving circuit substrate, a first adhesive member between the driving pad part and the first connecting pad part, and a second adhesive member between the panel pad part and the second connecting pad part. At least one of the first and second adhesive members is a conductive adhesive member including a polymer resin and a plurality of conductive particles including at least one of tin or indium.

Abstract: The disclosure provides a pull and a manufacturing method of the pull, which can mount an electronic component inside a handle part without damaging the electronic component and have favorable electronic functions. The pull of the disclosure is to be mounted on a slider for a slide fastener, and includes a ring part, an insertion part, the handle part, and the electronic component. The ring part is to be mounted on the slider. The insertion part is connected to the ring part for receiving an injection material. The handle part is formed sequentially on the insertion part by the injection material. The electronic component is mounted inside the handle part in a process in which the handle part is formed sequentially on the insertion part by the injection material.