Abstract: A deposition processing method includes a step of depositing deposits onto a substrate using a first plasma generated in a processing condition of depositing the deposits onto the substrate, which is basically a first processing condition, and a preceding step performed before the step of depositing the deposits onto the substrate, wherein, within the step of depositing the deposits transited from the preceding step, the processing condition is controlled so as to deposit less deposits than that in the first processing condition until a state of the first plasma is stabilized.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

Abstract: According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (NKey) that is hidden, includes a memory configured to store second key information (HKey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (SKey) by using the second key information (HKey) and the random number information. The authenticator is configured such that the second key information (HKey) is generated from the first key information (NKey) but the first key information (NKey) is not generated from the second key information (HKey).

Abstract: According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (NKey) that is hidden, includes a memory configured to store second key information (HKey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (SKey) by using the second key information (HKey) and the random number information. The authenticator is configured such that the second key information (HKey) is generated from the first key information (NKey) but the first key information (NKey) is not generated from the second key information (HKey).

Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.

Abstract: A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.

Abstract: A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.

Abstract: According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (NKey) that is hidden, includes a memory configured to store second key information (HKey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (SKey) by using the second key information (HKey) and the random number information. The authenticator is configured such that the second key information (HKey) is generated from the first key information (NKey) but the first key information (NKey) is not generated from the second key information (HKey).

Abstract: According to one embodiment, a semiconductor memory device includes a cell transistor coupled to a word line, a sense amplifier configured to output data based on a state of the cell transistor in response to a first signal asserted; and a controller configured to apply a voltage of a magnitude continuously rising to the word line, and periodically assert the first signal after a lapse of any selected one of a first time and a second time from the start of rise of the magnitude of the voltage. The first time is different from the second time.

Abstract: According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (NKey) that is hidden, includes a memory configured to store second key information (HKey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (SKey) by using the second key information (HKey) and the random number information. The authenticator is configured such that the second key information (HKey) is generated from the first key information (NKey) but the first key information (NKey) is not generated from the second key information (HKey).

Abstract: According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a cell transistor coupled to a word line, a sense amplifier configured to output data based on a state of the cell transistor in response to a first signal asserted; and a controller configured to apply a voltage of a magnitude continuously rising to the word line, and periodically assert the first signal after a lapse of any selected one of a first time and a second time from the start of rise of the magnitude of the voltage. The first time is different from the second time.

Abstract: According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (NKey) that is hidden, includes a memory configured to store second key information (HKey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (SKey) by using the second key information (HKey) and the random number information. The authenticator is configured such that the second key information (HKey) is generated from the first key information (NKey) but the first key information (NKey) is not generated from the second key information (HKey).

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N?1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N?1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.