Patents by Inventor Yuji Tada

Yuji Tada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230339994
    Abstract: A novel cyclic phosphazene compound that is represented by Formula (1) and is useful as a flame retardant of a resin material can enhance flame retardancy of the resin material and achieve good dielectric properties while suppressing deterioration in physical properties. In Formula (1), n is an integer of 3 to 8. R1 and R2 are (i) each independently a nitro group, either an alkyl group or an alkoxy group having 1 to 8 carbon atoms in which an alkyl group having 1 to 6 carbon atoms or an aryl group may be substituted, or an either aryl group or an aryloxy group having 6 to 20 carbon atoms in which an alkyl group having 1 to 6 carbon atoms or an aryl group may be substituted; or (ii) forming, in-between them, a saturated or an unsaturated cyclic structure that may be substituted with an alkyl group having 1 to 6 carbon atoms or a carbonyl group. a and b are each independently an integer of 0 to 4. The type of the oxaphosphorin ring-containing structure of each repeating unit is independent.
    Type: Application
    Filed: June 19, 2021
    Publication date: October 26, 2023
    Applicant: FUSHIMI PHARMACEUTICAL CO., LTD.
    Inventors: Yuji TADA, Atsushi SUNADA, Keiichiro UTSUMI
  • Publication number: 20200115527
    Abstract: The invention provides a flame retardant for a polyester based synthetic fiber structure comprising aminopentaphenoxycyclotriphosphazene, and a flame retardant treatment agent for a polyester based synthetic fiber structure comprising the flame retardant dispersed in a solvent in the presence of a surfactant.
    Type: Application
    Filed: June 16, 2018
    Publication date: April 16, 2020
    Applicants: DAIKYO CHEMICAL CO., LTD., FUSHIMI PHARMACEUTICAL CO., LTD.
    Inventors: Terufumu IWAKI, Shigeto KOYAMA, Yuji TADA
  • Patent number: 8796860
    Abstract: A semiconductor device includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a layer and another one of the ground lines extending from the one of the ground lines toward another direction in the layer, a first pad on the multi-layer wiring layer, and a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first pad and the second pad, and an insulation film covering the redistribution line.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
  • Patent number: 8436469
    Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
  • Patent number: 8405219
    Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: March 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
  • Patent number: 8289041
    Abstract: A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazunori Yamane, Takayuki Kurokawa, Yuji Tada, Hironori Nakamura, Manabu Kitabatake
  • Publication number: 20120241971
    Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.
    Type: Application
    Filed: June 7, 2012
    Publication date: September 27, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuji Tada, Tsuyoshi HIRAKAWA, Hironori NAKAMURA, Takayuki KUROKAWA
  • Patent number: 8237287
    Abstract: A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
  • Publication number: 20110241216
    Abstract: A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.
    Type: Application
    Filed: February 28, 2011
    Publication date: October 6, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
  • Patent number: 7777513
    Abstract: A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: August 17, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Manabu Kitabatake, Yuji Tada, Kouji Naganawa, Tsuyoshi Hirakawa, Ichiro Mizuguchi
  • Patent number: 7767739
    Abstract: A phosphazene compound, which can effectively enhance flame retardancy without deteriorating mechanical properties of a resin molded product, and is also less likely to deteriorate thermal reliability and dielectric properties, is represented by the formula (1) shown below. n represents an integer of 3 to 15. wherein A represents a group selected from the group consisting of an alkoxy group, an aryloxy group and a group having a cyanato group, and at least one is a group having a cyanato group, and an example of A is a cyanatophenyl-substituted phenyloxy group represented by the formula (4) shown below, and Y in the formula (4) represents O, S, SO2, CH2, CHCH3, C(CH3)2, C(CF3)2, C(CH3)CH2CH3 or CO.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: August 3, 2010
    Assignee: Fushimi Pharmaceutical Co., Ltd.
    Inventors: Yuji Tada, Takashi Inoue
  • Publication number: 20090167337
    Abstract: A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.
    Type: Application
    Filed: December 15, 2008
    Publication date: July 2, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Kazunori Yamane, Takayuki Kurokawa, Yuji Tada, Hironori Nakamura, Manabu Kitabatake
  • Publication number: 20090170983
    Abstract: A phosphazene compound, which can effectively enhance flame retardancy without deteriorating mechanical properties of a resin molded product, and is also less likely to deteriorate thermal reliability and dielectric properties, is represented by the formula (1) shown below. n represents an integer of 3 to 15. wherein A represents a group selected from the group consisting of an alkoxy group, an aryloxy group and a group having a cyanato group, and at least one is a group having a cyanato group, and an example of A is a cyanatophenyl-substituted phenyloxy group represented by the formula (4) shown below, and Y in the formula (4) represents O, S, SO2, CH2, CHCH3, C(CH3)2, C(CF3)2, C(CH3)CH2CH3 or CO.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 2, 2009
    Inventors: Yuji Tada, Takashi Inoue
  • Publication number: 20090015286
    Abstract: A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device.
    Type: Application
    Filed: June 20, 2008
    Publication date: January 15, 2009
    Inventors: Manabu Kitabatake, Yuji Tada, Kouji Naganawa, Tsuyoshi Hirakawa, Ichiro Mizuguchi
  • Patent number: 7345102
    Abstract: An epoxy resin composition for encapsulating optical semiconductor element, comprising the following (A) to (D): (A) an epoxy resin component comprising a novolak type epoxy resin having at least one of the biphenyl skeleton and naphthalene skeleton in one molecule in an amount of from 50 to 100% by weight of the total weight of the epoxy resin component, (B) a curing agent component comprising a novolak type phenol resin having at least one of the biphenyl skeleton and naphthalene skeleton in one molecule in an amount of from 50 to 100% by weight of the total weight of the curing agent component, (C) an organic phosphorus flame retarder, and (D) a curing catalyst, wherein the content of an organic phosphorus flame retarder as (C) is from 1.5 to 10% by weight based on the total weight of the epoxy resin composition.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: March 18, 2008
    Assignee: Nitto Denko Corporation
    Inventors: Hisataka Ito, Shinya Ota, Yuji Tada
  • Patent number: 7205345
    Abstract: A blending of a styrenic resin, and a flame retardant comprising a phenolic resin and a phosphazene compound to a polyalkylene arylate-series resin imparts flame retardancy to a polyalkylene arylate-series resin. The phosphazene compound is a cyclic phenoxyphosphazene compound, a linear phenoxyphosphazene compound, or a crosslinked phenoxyphosphazene compound. The obtained polyalkylene arylate-series resin composition has excellent heat resistance and high flame-retardancy without bleeding out the flame retardant.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: April 17, 2007
    Assignee: Polyplastics Co., Ltd.
    Inventors: Hatsuhiko Harashina, Shinya Yamada, Yuji Tada
  • Patent number: 7169836
    Abstract: A flame retardant comprising a phosphazene compound, a polyphenylene oxide-series resin, and if necessary a styrenic resin and/or a nitrogen-containing compound imparts flame retardancy to a polyalkylene arylate-series resin. The phosphazene compound comprises at least a crosslinked phenoxyphosphazene compound. The obtained polyalkylene arylate-series resin composition shows high flame-retardancy.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: January 30, 2007
    Assignee: Polyplastics Co., Ltd
    Inventors: Hatsuhiko Harashina, Shinya Yamada, Yuji Tada
  • Patent number: 6946578
    Abstract: An improved phenoxyphosphazene compound is produced by treating a phenoxyphosphazene compound with (a) at least one adsorbent selected from activated carbon, silica gel, activated alumina, activated clay, synthetic zeolite and macromolecular adsorbents, (b) at least one reagent selected from metal hydrides, hydrazine, hypochlorites, thiosulfates, dialkyl sulfuric acids, ortho esters, diazoalkanes, lactones, alkanesultones, epoxy compounds and hydrogen peroxide, or (c) both the adsorbent and reagent, thereby reducing the acid value of said phosphazene compound to lower than 0.025 mgKOH/g.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: September 20, 2005
    Assignee: Otsuka Chemical Co., Ltd.
    Inventors: Shinji Nakano, Yuji Tada, Tadao Yabuhara, Takashi Kameshima, Yoichi Nishioka, Hiroyuki Takase
  • Publication number: 20050148701
    Abstract: A blending of a styrenic resin, and a flame retardant comprising a phenolic resin and a phosphazene compound to a polyalkylene arylate-series resin imparts flame retardancy to a polyalkylene arylate-series resin. The phosphazene compound is a cyclic phenoxyphosphazene compound, a linear phenoxyphosphazene compound, or a crosslinked phenoxyphosphazene compound. The obtained polyalkylene arylate-series resin composition has excellent heat resistance and high flame-retardancy without bleeding out the flame retardant.
    Type: Application
    Filed: June 27, 2002
    Publication date: July 7, 2005
    Inventors: Hatsuhiko Harashina, Shinya Hamada, Yuji Tada
  • Patent number: 6905768
    Abstract: The epoxy resin of the invention comprises (A) an epoxy resin, (B) at least one member selected from the group consisting of a phenolic hydroxyl group-containing compound, a urea resin and a melamine resin, (C) a crosslinked phenoxyphosphazene compound, and (D) an inorganic filler powder, the amount of component (C) being in the range of 0.01 to 30 wt. % based on the total amount of components (A), (B) and (C), and the amount of component (D) being in the range of 60 to 98 wt. % based on the total amount of components (A), (B), (C) and (D). The epoxy resin composition of the invention and a molded product are halogen-free and antimony-free and are excellent in flame retardancy. When an element for an electronic part such as LSI and VLSI is encapsulated by the epoxy resin composition of the invention, the obtained electronic part is outstanding in heat resistance, moisture resistance, thermal impact resistance and like properties.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: June 14, 2005
    Assignee: Otsuka Chemical Co., Ltd.
    Inventors: Yuji Tada, Shinji Nakano