Abstract: A semiconductor memory device including:a data storage device having a plurality of memory cells each capable of storing a data and being selected by an address, first complementary data corresponding to the data in a selected memory cell being outputted to first complementary data lines;a first equalizer for short-circuiting and equalizing the first complementary data lines;an amplifier for receiving the first complementary data from the first complementary data lines, making large the difference between levels of the first complementary data, and outputting as second complementary data the levels to second complementary data lines;a second equalizer for short-circuiting and equalizing the second complementary data lines;a data latch circuit having latch units and switching means, the latch unit receiving and latching the second complementary data from the second complementary data lines and outputting as third complementary data the second complementary data to third complementary data lines, the switching