Abstract: A memory control apparatus includes a randomizer configured to: randomize write data output from an arithmetic processing apparatus, and output the randomized write data to a memory; a derandomizer configured to: derandomize data read from the memory, and generate derandomized read data when a flag included in the data read from the memory indicates the randomized write data; and a selector configured to: select the derandomized read data and output the selected derandomized read data to the arithmetic processing apparatus when the flag indicates the randomized write data, and select the data read from the memory and output the selected read data to the arithmetic processing apparatus when the flag indicates deleted data.

Abstract: A memory control apparatus includes a randomizer configured to: randomize write data output from an arithmetic processing apparatus, and output the randomized write data to a memory; a derandomizer configured to: derandomize data read from the memory, and generate derandomized read data when a flag included in the data read from the memory indicates the randomized write data; and a selector configured to: select the derandomized read data and output the selected derandomized read data to the arithmetic processing apparatus when the flag indicates the randomized write data, and select the data read from the memory and output the selected read data to the arithmetic processing apparatus when the flag indicates deleted data.

Abstract: A data transfer device includes a data transmitting circuit includes an error detection code generating unit generating an error detection code for detecting an error in the data, and a transmission unit transmitting the data and the error detection code together with retransmit enable information representing that corresponding data transmitted before the former data or transmitted next can be retransmitted, the data receiving circuit includes a reception unit receiving the transmitted data, the transmitted error detection code and the transmitted retransmit enable information, an error detection unit detecting the error in the received data based on the error detection code, an error data retaining unit retaining the data in which an error is detected when the reception unit receives the retransmit enable information, and an error data comparing unit that comparing the error detected data retained in the error data retaining unit with corresponding data that is retransmitted.

Abstract: A cache control device includes an entering unit, a first searching unit, a reading unit, a second searching unit, and a rewriting unit. The entering unit alternately enters, into a pipeline, a load request for reading a directory received from a processor and a store request for rewriting a directory received from the processor. When the first searching unit determines that the directory targeted by the load request is present in the first cache memory or the second cache memory, the reading unit reads the directory from the cache memory in which the directory is present. When the second searching unit determines that the directory targeted by the store request is present in the first cache memory, the rewriting unit rewrites the directory that is stored in the first cache memory.

Abstract: A directory cache control device includes a cache unit, a detection unit, a holding unit, a determination unit, and a control unit. The cache unit caches a directory indicating an information processing apparatus caching information that is stored in a memory. The detection unit detects an error in the directory in the cache unit. The holding unit holds a memory address of the memory where information associated with the directory where the error is detected is stored. The determination unit determines whether a memory address that is a target of the read request and the address that is being held by the holding unit match each other or not. The control unit controls coherency of the information that is a target of the read request, based on a directory of the information that is the target of the read request.

Abstract: A cache memory device including a cache memory that includes a plurality of entries and includes at least one block including data and a status representing a status of the data for each entry and a control unit that performs replacement of the data on each block of the cache memory, wherein the control unit includes a counter that counts the number of replacements by which the data is replaced in each entry for each entry and a switching unit that switches a replacement scheme of the data according to the number of replacements.

Abstract: A control information transmitting unit of an information processing unit transmits a control packet including control information and destination information that designates one or more information processing units as destinations of the control information. In the case where, in the received control packet, the information processing unit is designated as a destination of the control information, a control information receiving unit of the information processing unit imports the control information from the control packet, and modifies the control packet in such a manner that the destination information does not designate the information processing unit as a destination of the control information and transmits the modified control packet. On the other hand, if the information processing unit is not designated as a destination of the control information, the control information receiving unit simply transmits the received control packet.

Abstract: To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.

Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.

Abstract: An arbitration unit, when a blocking error disabling data from being output to a destination node from an output buffer occurs in any one of the destination nodes, determines an input buffer connected to the output buffer from within the input buffers including the input buffer retaining the data addressed to the destination node in which the blocking error occurs, and a connection switchover unit connects the determined input buffer to the output buffer of the destination node for the data retained in the input buffer.

Abstract: A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.

Abstract: An information processing system includes sets of multiple processors performing processing synchronously. The system includes: a ROM storing a firmware program activating the processors to a synchronized state; a RAM defined by one address map; a firmware copying section copying the firmware program in the ROM to the RAM, on system boot; and a RAM address register storing an address of the RAM and of a copy destination of the firmware program. The system further includes: a RAM address storing section storing the address of the RAM and of the copy destination of the firmware program; a loss-of-synchronism detection section detecting loss of synchronism of the processors; and an address replacing section referring to the RAM address register upon detection of the loss of synchronism, thereby replacing an address for reading the stored firmware program, with the address of the RAM and of the copy destination of the firmware program.

Abstract: A data transfer device includes a data transmitting circuit includes an error detection code generating unit generating an error detection code for detecting an error in the data, and a transmission unit transmitting the data and the error detection code together with retransmit enable information representing that corresponding data transmitted before the former data or transmitted next can be retransmitted, the data receiving circuit includes a reception unit receiving the transmitted data, the transmitted error detection code and the transmitted retransmit enable information, an error detection unit detecting the error in the received data based on the error detection code, an error data retaining unit retaining the data in which an error is detected when the reception unit receives the retransmit enable information, and an error data comparing unit that comparing the error detected data retained in the error data retaining unit with corresponding data that is retransmitted.

Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.

Abstract: A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.

Abstract: In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.

Abstract: In an information processing system loaded with a CPU having cache and a system controller having a copy of a tag of the cache (snoop tag), and the CPU not issuing replacement information about the cache tag, the number of WAYs of the snoop tags in the system controller is larger than the number of WAYs of the cache tags in the CPU to reduce a cache miss rate and suppress the degradation of performance by suppressing excess replacement of the cache tags in the CPU.

Abstract: A trace device for tracing data in an LSI includes a trace data storing unit that stores trace data, a trace target determination unit that determines whether to store trace data of one of a plurality of trace targets in the trace data storing unit based on an operating state of a system including the LSI and based on a failure occurrence report reported from any of the trace targets in response to an occurrence of an error in the trace target residing in the LSI and a trace target selection unit that selects the trace data to be stored in the trace data storing unit out of the trace data from the plurality of trace targets based on the determining by the trace target determination unit, and stores the selected trace data in the trace data storing unit.

Abstract: In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.

Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.