Abstract: A calculation resource control device includes an input unit to which a processing content specified by a user is input, an equivalent circuit preparation unit that collects candidates for an equivalent circuit that is a processing circuit having a function of executing a part of the processing content to output an equivalent circuit candidate group, and a function chain creation unit that determining a processing execution circuit from the equivalent circuit candidate group on the basis of a predetermined reference, determines a connection order of the processing execution circuit, and outputs a function chain for executing the processing content.

Abstract: A transfer processing device includes an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The arithmetic instruction number acquisition circuit acquires a transfer instruction number corresponding to transfer information which is information related to the next transfer destination of an arithmetic instruction. The buffer circuit is arranged between the arithmetic instruction number acquisition circuit and the transfer information acquisition circuit, and temporarily stores and relays the arithmetic instruction and the arithmetic instruction number supplied from the arithmetic instruction number acquisition circuit to the transfer information acquisition circuit. The transfer information acquisition circuit acquires transfer information on the basis of the arithmetic instruction number, and gives the acquired transfer information to the arithmetic instruction.

Abstract: Each NIC performs an aggregation calculation of data output from each processor in a normal order including a head NIC located at a head position of a first pipeline connection, an intermediate NIC located at an intermediate position, and a tail NIC located at a tail position, and when the aggregation calculation in the tail NIC is completed, each NIC starts distribution of an obtained aggregation result, distributes the aggregation result in a reverse order including the tail NIC, the intermediate NIC, and the head NIC, and outputs the aggregation result to the processor of the communication interface.

Abstract: In an NFV system, a protocol processor that receives a packet from an external network, a calculator that implements NFV for performing predetermined processing on the received packet, and an ANN calculator that performs processing using an ANN in the processing of the NFV are mounted on an NIC.

Abstract: A network card has a plurality of buffers each having different physical performances including a memory access speed or a storage capacity, and a buffer control circuit selects one buffer to be a packet storage destination from among the plurality of buffers on the basis of a priority or a service quality of a packet specified from header information of the packet received by a physical port and the physical performances of the plurality of buffers.

Abstract: In a network interface card, a buffer is provided with a plurality of queues corresponding to packet priority levels, a packet processing circuit stores a packet in a queue in the buffer corresponding to the priority level obtained from a packet received by a physical port, and a control circuit sequentially selects a queue in the buffer on the basis of the packet priority level and allocates a packet read from the selected queue to a computation/processing circuit.

Abstract: A neural architecture search system includes a deployment constraint management unit that converts a first constraint condition that defines a constraint of a system that implements a neural network into a second constraint condition that defines a constraint of a parameter that prescribes an architecture of the neural network, a learning engine unit that performs learning of the neural network under a search condition and calculates inference accuracy in a case where the learned neural network is used, and a model modification unit that causes the learning engine unit to perform the learning and the calculation of the inference accuracy while changing the architecture of the neural network on the basis of the inference accuracy and the second constraint condition so as to obtain the best inference accuracy.

Abstract: Individual distributed processing nodes packetize distributed data for each weight of a neural network of a learning object in an order of a number of the weight, transmit the distributed data to an aggregation processing node, acquire aggregation data transmitted from the node in order, and update the weight of the neural network. The node acquires the transmitted distributed data, packetizes the aggregation data for which the distributed data of all the distributed processing nodes is aggregated for each weight, and transmits the aggregation data to the individual nodes. The individual nodes monitor an unreceived data amount which is a difference between data amounts of the transmitted distributed data and the acquired aggregation data, and when the unreceived data amount becomes equal to or larger than a threshold Ma, stops transmission of the distributed data until the unreceived data amount becomes equal to or smaller than a threshold Mb (Mb<Ma).

Abstract: An inference processing device uses a learned neural network to infer a feature of input data, the inference processing device including: a first storage unit that stores the input data; a second storage unit that stores a weight of the learned neural network; a data filtering unit that extracts only specific input data from pieces of the input data; and an inference operation unit that uses the specific input data extracted by the data filtering unit and the weight as inputs, performs inference operation of the learned neural network, and infers the feature of the input data.

Abstract: A computer system according to the present invention includes N (N is an integer of 2 or more) data output devices, a transmission control device, and an arithmetic device, in which the arithmetic device executes predetermined arithmetic processing on data collected from the N data output devices via a communication network connecting the data output devices and the arithmetic device to each other, the transmission control device controls transmission timing of data output from the N data output devices according to a processing content of the predetermined arithmetic processing executed by the arithmetic device, and the N data storage devices are configured to output the data on the basis of the transmission timing notified by the transmission control device.

Abstract: A distributed processing node includes a computing device that calculates gradient data of a loss function from an output result obtained by inputting learning data to a learning target model, an interconnect device that aggregates gradient data between the distributed processing node and other distributed processing nodes, a computing function unit that is provided in a bus device and performs processing of gradient data from the computing device, and a DMA controller that controls DMA transfer of gradient data between the computing device and the bus device and DMA transfer of gradient data between the bus device and the interconnect device.

Abstract: A distributed deep learning system includes nodes (1-n, n=1, . . . , 4) and a network. The node (1-n) includes GPUs (11-n-1 and 11-n-2), and an FPGA (12-n). The FPGA (12-n) includes a plurality of GPU reception buffers, a plurality of network transmission buffers that store data transferred from the GPU reception buffers, a plurality of network reception buffers that store aggregated data received from other nodes, and a plurality of GPU transmission buffers that store data transferred from the network reception buffers. The GPUs (11-n-1 and 11-n-2) DMA-transfer data to the FPGA (12-n). The data stored in the GPU transmission buffers is DMA-transferred to the GPUs (11-n-1 and 11-n-2).

Abstract: A distributed processing system including a plurality of distributed systems, transmission media connecting the plurality of distributed systems and a control node connected to the plurality of distributed systems, wherein each of the distributed systems includes one or more distributed nodes constituting a distributed node group and a piece of electric equipment accommodating the distributed node group. Each of the distributed nodes includes interconnects to connect to any of the transmission media and/or other distributed nodes; and the control node determines, based on a quantity of computational resources required for a job, distributed systems, distributed systems and distributed nodes in the distributed systems to execute the job from the plurality of distributed systems, selects a connection path for data to be processed among the distributed systems, and provides information about an interconnect connection path for the distributed nodes to execute the job.

Abstract: A distributed processing system to which a plurality of distributed nodes are connected, each of the distributed nodes including a plurality of arithmetic devices and an interconnect device, wherein, in the interconnect device and/or the arithmetic devices of one of the distributed nodes, memory areas are assigned to each job to be processed by the distributed processing system, and direct memory access between memories for processing the job is executed at least between interconnect devices, between arithmetic devices or between an interconnect device and an arithmetic device.

Abstract: A distributed deep learning system includes a plurality of computation nodes mutually connected through a communication network, wherein each of the plurality of computation nodes includes a network processing unit including: a reception section that receives an OAM packet indicating states of the plurality of computation nodes; an OAM processing section that makes a record, in the OAM packet received by the reception section, of whether or not a partial arithmetic operation result is outputted from an arithmetic operation unit of the own node; and a transmission section that transmits the OAM packet including the record made by the OAM processing section to another computation node, wherein the OAM processing section, depending on the state of the other computation node indicated by the OAM packet, causes the transmission section to transmit the partial arithmetic operation result stored in a storage unit to the other computation node.

Abstract: Provided is a distributed deep learning system including a plurality of distributed processing nodes, in which each of the plurality of distributed processing nodes includes a header reading unit configured to read pieces of layer information of headers of a first data frame that has arrived at an own node and a second data frame that has arrived next, and in which the pieces of layer information are compared with each other, calculation processing is executed for a data frame including data that belongs to a layer closer to an input layer, and calculation processing for a data frame including data that belongs to a layer closer to an output layer is skipped.

Abstract: A distributed deep learning system includes a plurality of calculation nodes connected to one another via a communication network. Each of the plurality of calculation nodes includes a computation unit that calculates a matrix product included in computation processing of a neural network and outputs a partial computation result, a storage unit that stores the partial computation result, and a network processing unit including a transmission unit that transmits the partial computation result to another calculation node, a reception unit that receives a partial computation result from another calculation node, an addition unit that obtains a total computation result, which is a sum of the partial computation result stored in the storage unit and the partial computation result from another calculation node, a transmission unit that transmits the total computation result to another calculation node, and a reception unit that receives a total computation result from another calculation node.

Abstract: An embodiment is a computer including a plurality of accelerators, a computer for distributed processing includes a plurality of accelerators to each of which a part of a neural network is assigned and each of which is configured to derive a learning result based on input data and update each parameter value included in the part of the neural network by using the learning result; a plurality of network interface circuits each of which is configured to transmit and receive information on learning including the learning result via a network, and an arithmetic processing unit that is configured to control the plurality of accelerators and the plurality of network interface circuits to cause each of the plurality of accelerators to derive a learning result based on input data and to cause the plurality of network interface circuits to transmit and receive information on learning including the learning result.

Abstract: The inference processing apparatus includes an inference calculator that performs calculation of a neural network based on input data xt of each consecutive time step and weights W of a trained neural network to infer features of the input data xt and also includes a memory that stores input data xt and weight W, a temporary memory that stores an output ht?1 of an inference result of an immediately previous time step, and a switching controller that controls switching between a first operation mode TM1 in which the inference calculator performs calculation of the neural network based on the input data xt, the weight W, and the output ht?1, at each time step and a second operation mode TM2 in which the inference calculator performs calculation of the neural network based on the input data xt and the weight W at each time step.

Abstract: An inference processing apparatus infers a feature of input data X using a trained neural network and includes a storage unit that stores the input data X and a weight W of the trained neural network, a setting unit that sets a bit accuracy of inference calculation and a number of units of the trained neural network based on an input inference accuracy, and an inference calculation unit that performs an inference calculation of the trained neural network, taking the input data X and the weight W as inputs, based on the bit accuracy of the inference calculation and the number of units set by the setting unit to infer the feature of the input data X.