Patents by Inventor Yuki Igawa

Yuki Igawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor element and wafer level chip size package therefor
    Patent number: 7830011
    Abstract: A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: November 9, 2010
    Assignee: Yamaha Corporation
    Inventors: Kentaro Nomoto, Yuki Igawa, Hiroshi Saitoh, Takashi Sato, Toshio Ohashi, Yoshihiro Ohkura
  • Semiconductor element and wafer level chip size package therefor
    Publication number: 20050199995
    Abstract: A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.
    Type: Application
    Filed: March 10, 2005
    Publication date: September 15, 2005
    Inventors: Kentaro Nomoto, Yuki Igawa, Hiroshi Saitoh, Takashi Sato, Toshio Ohashi, Yoshihiro Ohkura