Patents by Inventor Yuki Mizutani
Yuki Mizutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111440Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: SanDisk Technologies LLCInventors: Yuki Mizutani, Kazutaka Yoshizawa, Kiyokazu Shishido, Eiichi Fujikura
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Publication number: 20240102957Abstract: In an electrochemical gas sensor (10), a first sensing element (21) is stored in a first storage portion (31). A moisture permeable film (24) is disposed in a first introduction inlet (31A) of the first storage portion (31). The moisture permeable film (24) substantially prevents a to-be-detected gas from permeating therethrough. A second sensing element (22) is disposed in a space into which water vapor and the to-be-detected gas contained in a target gas flow. In such a configuration, the electrochemical gas sensor (10) is capable of detecting a to-be-detected gas having a concentration of 0 or more and 1 ppm or less.Type: ApplicationFiled: March 8, 2022Publication date: March 28, 2024Inventors: Shinichiro KITO, Masayuki SEGAWA, Takahiro YOKOYAMA, Junya IMAIZUMI, Yuki MIZUTANI, Masahiro TANAKA, Yoshiko KUMAGAI
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Publication number: 20240080185Abstract: A result confirmation unit (204) computes a state space probability that is a probability that a verification target device (300) has not correctly prepared a state space having a quantum state stored therein, a Pauli measurement probability that is a probability that the verification target device (300) has not correctly performed Pauli Z measurement and Pauli X measurement, and a magic state probability that is a probability that the verification target device (300) has not generated a magic state of CCZ. Then, using the state space probability, the Pauli measurement probability, and the magic state probability, the result confirmation unit (204) computes a degree of approximation between a quantum state and the magic state of CCZ at the verification target device (300) and measurement accuracies of the Pauli Z measurement and the Pauli X measurement on the quantum state at the verification target device (300).Type: ApplicationFiled: October 31, 2023Publication date: March 7, 2024Applicants: Mitsubishi Electric Corporation, NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Akihiro MIZUTANI, Ryo HIROMASA, Yusuke AIKAWA, Yuki TAKEUCHI, Seiichiro TANI
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Publication number: 20230367944Abstract: The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: SanDisk Technologies LLCInventors: Yuki Mizutani, Masaaki Higashitani
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Patent number: 11813920Abstract: Provided is a piping system for an air conditioner installed in a vehicle that can achieve appropriate weight reduction while ensuring appropriate pressure resistance as the piping system as a whole. A circulation path that connects component devices of an air conditioner (8) in an annular shape to circulate a refrigerant (C) is formed by each pipe body extending between the component devices. At least one of the pipe bodies includes: a resin hose (2) embedded with a non-metal reinforcing material (3f) or a resin pipe (5) embedded with a non-metal reinforcing material (6f), and the resin pipe bodies (2), (5) are employed in 50% or more of a total length of each of the pipe bodies constituting the circulation path.Type: GrantFiled: March 24, 2020Date of Patent: November 14, 2023Assignee: The Yokohama Rubber Co., Ltd.Inventors: Gang Hou, Hiroaki Shibano, Jiro Watanabe, Susumu Hatanaka, Naoshi Yamaguchi, Mie Okura, Ikuma Yusa, Shusaku Tomoi, Tomohide Saita, Hiroyuki Wakamatsu, Ryuhei Suzuki, Yuki Mizutani, Nobuaki Kuribayashi, Hiroshi Shintani, Kazuto Yamakawa
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Publication number: 20230282288Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line. During some read operations, this allows the memory device to operate with lower power requirements.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Deepanshu Dutta, Ohwon Kwon, James Kai, Yuki Mizutani
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Publication number: 20230044232Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.Type: ApplicationFiled: December 20, 2021Publication date: February 9, 2023Inventors: James KAI, Yuki MIZUTANI, Hisakazu OTOI, Masaaki HIGASHITANI, Hiroyuki OAGAWA
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Patent number: 11569259Abstract: A memory die can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures vertically extending through the alternating stack. A first layer stack within the alternating stack includes a first staircase region in which the first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide first stepped surfaces. A second layer stack within the alternating stack includes a second staircase region in which the second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide second stepped surfaces. The second layer stack can be more distal from the substrate than the first layer stack. Contact via structures can be formed from the top side and the bottom side of the alternating stack.Type: GrantFiled: August 5, 2020Date of Patent: January 31, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Yuki Mizutani, Masaaki Higashitani
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Publication number: 20220399358Abstract: A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.Type: ApplicationFiled: October 11, 2021Publication date: December 15, 2022Inventors: Yuki MIZUTANI, Fumiaki TOYAMA, Masaaki HIGASHITANI
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Publication number: 20220399362Abstract: A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.Type: ApplicationFiled: June 15, 2021Publication date: December 15, 2022Inventors: Yuki MIZUTANI, Fumiaki TOYAMA, Masaaki HIGASHITANI
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Publication number: 20220355643Abstract: Provided is a piping system for an air conditioner installed in a vehicle that can achieve appropriate weight reduction while ensuring appropriate pressure resistance as the piping system as a whole. A circulation path that connects component devices of an air conditioner (8) in an annular shape to circulate a refrigerant (C) is formed by each pipe body extending between the component devices. At least one of the pipe bodies includes: a resin hose (2) embedded with a non-metal reinforcing material (3f) or a resin pipe (5) embedded with a non-metal reinforcing material (6f), and the resin pipe bodies (2), (5) are employed in 50% or more of a total length of each of the pipe bodies constituting the circulation path.Type: ApplicationFiled: March 24, 2020Publication date: November 10, 2022Inventors: Gang HOU, Hiroaki SHIBANO, Jiro WATANABE, Susumu HATANAKA, Naoshi YAMAGUCHI, Mie OKURA, Ikuma YUSA, Shusaku TOMOI, Tomohide SAITA, Hiroyuki WAKAMATSU, Ryuhei SUZUKI, Yuki MIZUTANI, Nobuaki KURIBAYASHI, Hiroshi SHINTANI, Kazuto YAMAKAWA
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Patent number: 11404123Abstract: A non-volatile memory includes a non-volatile memory array comprising blocks of non-volatile memory cells, bit lines connected to the memory cells and word lines connected to the memory cells. Word line switch transistors connect the word lines to voltage sources. The word line switch transistors are positioned in triple wells. Multiple triple wells are utilized and the word line switch transistors are grouped into triple wells based on word line voltage ranges used during the programming process. In one embodiment, for a given block, the word line switch transistors connected to data word lines are positioned in a first triple well and the word line switch transistors connected to selection and dummy word lines are positioned in a second triple well. This structure allows the triple wells to be biased differently.Type: GrantFiled: April 15, 2021Date of Patent: August 2, 2022Assignee: SanDisk Technologies LLCInventors: Shiqian Shao, Fumiaki Toyama, Yuki Mizutani, Mohan Dunga, Peter Rabkin
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Patent number: 11355486Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.Type: GrantFiled: October 5, 2020Date of Patent: June 7, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Yuki Mizutani, Masaaki Higashitani, James Kai
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Publication number: 20220045089Abstract: A memory die can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures vertically extending through the alternating stack. A first layer stack within the alternating stack includes a first staircase region in which the first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide first stepped surfaces. A second layer stack within the alternating stack includes a second staircase region in which the second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide second stepped surfaces. The second layer stack can be more distal from the substrate than the first layer stack. Contact via structures can be formed from the top side and the bottom side of the alternating stack.Type: ApplicationFiled: August 5, 2020Publication date: February 10, 2022Inventors: Yuki MIZUTANI, Masaaki HIGASHITANI
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Patent number: 11211370Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.Type: GrantFiled: January 28, 2020Date of Patent: December 28, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Jee-Yeon Kim, Yuki Mizutani, Fumiaki Toyama
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Patent number: 11114459Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.Type: GrantFiled: November 6, 2019Date of Patent: September 7, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Takaaki Iwai, Hirofumi Tokita, Yoshitaka Otsu, Fumiaki Toyama, Yuki Mizutani
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Patent number: 11081443Abstract: A first vertically alternating sequence of first insulating layers and first spacer material layers and a first-tier retro-stepped dielectric material portion are formed over a substrate. The first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers. A second vertically alternating sequence of second insulating layers and second spacer material layers and a second-tier retro-stepped dielectric material portion are formed over the first vertically alternating sequence and the first-tier retro-stepped dielectric material portion. The second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers. An opening is formed through the second vertically alternating sequence over the first-tier retro-stepped dielectric material portion, and is filled with a dielectric well structure.Type: GrantFiled: March 24, 2020Date of Patent: August 3, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Yuki Mizutani, Masayuki Hiroi, Fumiaki Toyama
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Publication number: 20210233900Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.Type: ApplicationFiled: January 28, 2020Publication date: July 29, 2021Inventors: Jee-Yeon KIM, Yuki MIZUTANI, Fumiaki TOYAMA
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Patent number: 11011209Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.Type: GrantFiled: October 1, 2019Date of Patent: May 18, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Jee-Yeon Kim, Kwang-Ho Kim, Yuki Mizutani, Fumiaki Toyama
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Publication number: 20210134827Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.Type: ApplicationFiled: November 6, 2019Publication date: May 6, 2021Inventors: Takaaki IWAI, Hirofumi TOKITA, Yoshitaka OTSU, Fumiaki TOYAMA, Yuki MIZUTANI