Patents by Inventor Yuki YAKUSHIGAWA

Yuki YAKUSHIGAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230037409
    Abstract: In a semiconductor device, a semiconductor substrate has an IGBT region and a FWD, and includes a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region. The collector layer includes an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer. Alternatively, the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer, and has an area density of 3.5×1012 cm?2 or less.
    Type: Application
    Filed: October 25, 2022
    Publication date: February 9, 2023
    Inventors: Masanori MIYATA, Shuji YONEDA, Masaru SENOO, Yuki YAKUSHIGAWA
  • Publication number: 20220181471
    Abstract: A semiconductor device includes an IGBT region in which an IGBT element is formed and an FWD region in which an FWD element is formed. The IGBT region includes a first region and a second region different from the first region. The FWD region and the first region of the IGBT region have a carrier extraction portion that facilitates extraction of carriers injected from a second electrode compared to the second region when a forward bias for causing the FWD element to operate as a diode is applied between a first electrode and the second electrode.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: MASANORI MIYATA, YUUMA KAGATA, YUKI YAKUSHIGAWA, MASARU SENOO, HIROSHI HOSOKAWA, TAKAYA NAGAI
  • Publication number: 20210217845
    Abstract: A semiconductor device has a drift layer, a base layer, an emitter region, a gate insulation film, a gate electrode, a collector layer, a field stop layer, a first electrode and a second electrode. The base layer is disposed on the drift layer. The emitter region is disposed on a surface layer portion of the base layer. The gate insulation film is disposed between the drift layer and the emitter layer. The gate electrode is disposed on the gate insulation film. The collector layer is disposed at a portion of the drift layer opposite to the base layer. The field stop layer is disposed between the collector layer and the drift layer. The field stop layer has a higher carrier concentration than the drift layer. The first electrode is electrically connected to the base layer and the emitter region. The second electrode is electrically connected to the collector layer.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 15, 2021
    Inventors: MASANORI MIYATA, SHUJI YONEDA, YUKI YAKUSHIGAWA, MASARU SENOO
  • Patent number: 9735150
    Abstract: A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 15, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya Iwasaki, Satoru Kameyama, Yuki Yakushigawa
  • Patent number: 9570353
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: February 14, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru Kameyama, Shinya Iwasaki, Yuki Yakushigawa
  • Publication number: 20170033099
    Abstract: A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.
    Type: Application
    Filed: June 6, 2016
    Publication date: February 2, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya IWASAKI, Satoru KAMEYAMA, Yuki YAKUSHIGAWA
  • Publication number: 20170025310
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 26, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru KAMEYAMA, Shinya IWASAKI, Yuki YAKUSHIGAWA