Patents by Inventor Yukihiro Imura
Yukihiro Imura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923550Abstract: The preset disclosure provides a catalyst layer that has a small contact resistance with a gas diffusion layer and excellent gas diffusion properties. The catalyst layer for a fuel cell has a uniform thickness and includes fibrous conductive members and catalyst particles. The fibrous conductive members are inclined relative to a surface direction of the catalyst layer, and a lengthwise direction of the fibrous conductive members, on average, matches a first direction.Type: GrantFiled: December 26, 2018Date of Patent: March 5, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takeshi Minamiura, Hitoshi Ishimoto, Shinichiro Imura, Kazuya Yamasaki, Yukihiro Shimasaki
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Patent number: 10388618Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.Type: GrantFiled: February 11, 2019Date of Patent: August 20, 2019Assignee: ABLIC Inc.Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
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Publication number: 20190189575Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Inventors: Takeshi MORITA, Shinjiro Kato, Masaru Akino, Yukihiro Imura
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Patent number: 10297562Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.Type: GrantFiled: March 8, 2018Date of Patent: May 21, 2019Assignee: ABLIC INC.Inventors: Kaku Igarashi, Shinjiro Kato, Hisashi Hasegawa, Masaru Akino, Yukihiro Imura
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Patent number: 10249584Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.Type: GrantFiled: March 8, 2018Date of Patent: April 2, 2019Assignee: ABLIC INC.Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
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Publication number: 20180269169Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.Type: ApplicationFiled: March 8, 2018Publication date: September 20, 2018Inventors: Takeshi MORITA, Shinjiro KATO, Masaru AKINO, Yukihiro IMURA
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Publication number: 20180269170Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.Type: ApplicationFiled: March 8, 2018Publication date: September 20, 2018Inventors: Kaku IGARASHI, Shinjiro KATO, Hisashi HASEGAWA, Masaru AKINO, Yukihiro IMURA
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Patent number: 9917055Abstract: A corrosion-resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. An array of intersecting metal lines forming windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent entry of moisture.Type: GrantFiled: March 10, 2016Date of Patent: March 13, 2018Assignee: SII Semiconductor CorporationInventors: Yukihiro Imura, Yoshitaka Kimura, Masaru Akino
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Patent number: 9818691Abstract: A corrosion resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. A metal lattice having a plurality of windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. Alternatively, a metal array having a plurality of independent light-shielding portions may be disposed over the fuse elements to prevent the laser light from adversely affecting circuitry on the front surface side of the semiconductor device.Type: GrantFiled: March 10, 2016Date of Patent: November 14, 2017Assignee: SII Semiconductor CorporationInventors: Yukihiro Imura, Yoshitaka Kimura, Masaru Akino
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Publication number: 20160268196Abstract: Provided is a corrosion resistant semiconductor device including a fuse element that can be cut by laser light. In the semiconductor device, an upper portion of the fuse element is covered with a porous insulating film so that, when laser light radiated from a rear surface of a semiconductor substrate is collected at the fuse element, the fuse element may generate heat, expand, and rupture. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent moisture from coming therein.Type: ApplicationFiled: March 10, 2016Publication date: September 15, 2016Inventors: Yukihiro IMURA, Yoshitaka KIMURA, Masaru AKINO
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Publication number: 20160268197Abstract: Provided is a corrosion resistant semiconductor device including a fuse element that can be cut by laser light. A silicon nitride film is formed above the fuse element via a metal lattice and an interlayer film left therein so that, when laser light radiated from a rear surface of a semiconductor substrate is collected at the fuse element, the fuse element may generate heat, expand, and rupture. The silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent moisture from coming therein.Type: ApplicationFiled: March 10, 2016Publication date: September 15, 2016Inventors: Yukihiro IMURA, Yoshitaka KIMURA, Masaru AKINO
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Patent number: 5401991Abstract: A nonvolatile semiconductor memory is comprised of a semiconductor substrate composed of N-type silicon, a pair of source and drain regions having opposite electroconductivity to that of the semiconductor substrate and being formed in a surface region of the semiconductor substrate in spaced relation to each other to define therebetween a channel region, a gate insulating film formed on the channel region, a floating gate electrode formed on the gate insulating film over the channel region and composed of N-type polysilicon, and an insulating layer formed to cover the floating gate electrode. The floating gate electrode is composed of the N-type polysilicon effective to reduce the thickness of adjacent gate insulating film below 500 .ANG. to thereby significantly micronize the dimension of memory.Type: GrantFiled: June 5, 1989Date of Patent: March 28, 1995Assignee: Seiko Instruments Inc.Inventor: Yukihiro Imura
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Patent number: 5122847Abstract: A non-volatile semiconductor memory device is comprised of a floating gate electrode disposed on and electrically insulated from a semiconductor substrate for storing electric charge. A tunnel insulating film is disposed in contact with the floating gate electrode to inject and extract the electric charge to and from the floating gate electrode in the form of an electric tunnel current flowing through the tunnel insulating film. The tunnel insulating film is composed of silicon oxide chemically-vapor-deposited at a temperature between 700.degree. C. and 900.degree. C. from the vapor mixture of dichlorosilane and dinitrogen monoxide on the order of 100 .ANG. thickness to thereby establish a breakdown current density more than 1.0 A/cm.sup.2.Type: GrantFiled: September 7, 1988Date of Patent: June 16, 1992Assignee: Seiko Instruments & Electronics Ltd.Inventors: Masaaki Kamiya, Yukihiro Imura, Katsuyuki Takahashi
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Patent number: 5070386Abstract: A passivation layer covering a metal wire and semiconductor surface of a semiconductor integrated circuit composed of a metal-oxide-semiconductor (MOS) type transistor is a double-layer comprising a silicon nitride (P-SiN) layer formed by plasma CVD method and a phosphorus silicide glass (PSG) layer beneath the silicon nitride layer, and the P-SiN layer has a vacant region (a window) at the portion more than 20 .mu.m and less than 100 .mu.m away from an edge of a gate oxide layer of the transistor.Type: GrantFiled: July 30, 1990Date of Patent: December 3, 1991Assignee: Seiko Instruments Inc.Inventor: Yukihiro Imura