Patents by Inventor Yukihiro Katsumata

Yukihiro Katsumata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934003
    Abstract: A planar light source includes: a support member; a light guide member disposed on the support member and having a light source positioning part; and a light source disposed on the support member while being in the light source positioning part of the light guide member. The support member includes: an insulation base having a first face positioned closer to the light source and a second face positioned opposite the first face, a first conductive layer disposed on the first face of the insulation base and electrically connected to the light source, an adhesive layer disposed on and in contact with the first face of the insulation base and the first conductive layer, and a light reflecting sheet disposed on the adhesive layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 19, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Yukihiro Miura, Masaaki Katsumata, Ryohei Yamashita, Takashi Matsuo
  • Patent number: 5951683
    Abstract: One of processors connected effectively to a system is allocated to a master processor and the other remaining processors are allocated to slave processors. Each processor compares the self processor number of a processor number register and the processor number of the other processor of a processor effective register. For example, when the self processor number is smallest as compared with the other processor numbers, it is recognized that the self processor is a master processor. A master initialization diagnosing process after completion of the allocation is monitored by the slave processor. When an abnormality of the master processor is recognized, a degeneration to disconnect the master processor from the system is executed and is again reconstructed by the allocating process of master/slaves. Even when an abnormality occurs in the master processor, the operation in which the system was degenerated can be executed until the minimum construction in which two or more processors normally operate.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 14, 1999
    Assignees: Fujitsu Limited, PFU Limited
    Inventors: Kazuhiro Yuuki, Yukihiro Katsumata, Takeo Tabata, Shinichiro Nakamura