Patents by Inventor Yukihiro Yagi

Yukihiro Yagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9511143
    Abstract: The invention provides aqueous liquid pharmaceutical compositions comprising arbekacin and chloride ions. The compositions are well tolerable for use in a method for treatment or prevention of a disease of the upper or lower respiratory tract, wherein the composition is aerosolized and inhaled by the patient. Furthermore, the invention provides arbekacin hydrochloride.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: December 6, 2016
    Assignees: Meiji Seika Pharma Co., Ltd., PARI Pharma GmbH
    Inventors: Manfred Keller, Yukihiro Yagi, Masashi Tanaka, Toshie Sugano, Kuniko Shoji, Nao Sano, Michael Hahn, Roman Egle
  • Publication number: 20150173185
    Abstract: A circuit board structure and a manufacturing method for a circuit board that ensures an electrical connection between a metal foil and a projection without using a conductive adhesive and is less likely to cause a decrease in the reliability of the connection due to the interlayer separation or the like is provided. A circuit board includes an insulating layer, a lower main surface wiring pattern and an upper main surface wiring pattern disposed on either side of the insulating layer, and an interlayer connection conductor passing through the insulating layer in a thickness direction and electrically connecting to the lower main surface wiring pattern and the upper main surface wiring pattern. The interlayer connection conductor is formed integrally with the lower main surface wiring pattern, and is bonded to the upper main surface wiring pattern via an intermetallic compound.
    Type: Application
    Filed: March 2, 2015
    Publication date: June 18, 2015
    Inventors: Satoshi Ito, Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yuki Yamamoto
  • Patent number: 9044728
    Abstract: An ozone generating element includes a laminated body including stacked dielectric layers. A discharge electrode is provided on a first of the dielectric layers. An induction electrode is provided on a second of the dielectric layers that is opposed to the discharge electrode with the first dielectric layer interposed therebetween. A protective layer is arranged on the first dielectric layer so as to cover the discharge electrode, and includes a glass ceramic.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: June 2, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tetsuo Kanamori, Yukihiro Yagi, Takahiro Takada, Toshiyuki Miyamoto
  • Patent number: 9030005
    Abstract: In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yasutaka Sugimoto, Takahiro Takada
  • Patent number: 8975743
    Abstract: In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: March 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yasutaka Sugimoto, Takahiro Takada
  • Publication number: 20140343005
    Abstract: The invention provides aqueous liquid pharmaceutical compositions comprising arbekacin and chloride ions. The compositions are well tolerable for use in a method for treatment or prevention of a disease of the upper or lower respiratory tract, wherein the composition is aerosolized and inhaled by the patient. Furthermore, the invention provides arbekacin hydrochloride.
    Type: Application
    Filed: August 3, 2012
    Publication date: November 20, 2014
    Applicants: PARI PHARMA GMBH, MEIJI SEIKA PHARMA CO., LTD.
    Inventors: Manfred Keller, Yukihiro Yagi, Masashi Tanaka, Toshie Sugano, Kuniko Shoji, Nao Sano, Michael Hahn, Roman Egle
  • Publication number: 20140118977
    Abstract: A wiring board includes an insulating layer, and an upper wiring pattern and a lower wiring pattern arranged with the insulating layer interposed therebetween. A truncated cone-shaped projection is integral with the lower wiring pattern so as to project at the upper wiring pattern side, and a truncated cone-shaped projection is integral with the upper wiring pattern so as to project at the lower wiring pattern side. Bonding end portions of the projections are bonded to each other to form an inter-layer connection conductor. The inter-layer connection conductor conducts the upper wiring pattern and the lower wiring pattern.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi ITO, Yoichi MORIYA, Tetsuo KANAMORI, Yukihiro YAGI, Yuki YAMAMOTO
  • Publication number: 20140022750
    Abstract: A circuit board includes an insulating layer with a surface on which a semiconductor element is to be mounted and wiring portions that are located on the insulating layer. The wiring portions includes upper wiring portions, lower wiring portions, and interlayer wiring portions. The upper wiring portions, the lower wiring portions, and the interlayer wiring portions are integrally defined by a single copper sheet. With this configuration, a circuit board capable of withstanding a large current and a method of manufacturing the circuit board are provided.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 23, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi MORIYA, Satoshi ITO, Tetsuo KANAMORI, Yukihiro YAGI, Yuki YAMAMOTO
  • Publication number: 20140009899
    Abstract: A wiring substrate includes an insulating layer, an upper wiring pattern, and a lower wiring pattern, the wiring patterns sandwiching the insulating layer. The lower wiring pattern includes an interlayer connecting conductor integral therewith and projecting toward the upper wiring pattern for electrical connection to the upper wiring pattern. The interlayer connecting conductor is joined to the upper wiring pattern so as to penetrate into the upper wiring pattern beyond a joining interface between the insulating layer and the upper wiring pattern. Thus, the wiring substrate adaptable for a large current is provided without causing degradation of reliability in connection, which may occur by cracking, disconnection, interlayer peeling-off, etc.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 9, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi ITO, Yoichi MORIYA, Tetso KANAMORI, Yukihiro YAGI, Yuki YAMAMOTO
  • Patent number: 7211732
    Abstract: A cable connecting structure, which includes a cable accommodating box comprising: a box main body in which a connected portion of two cables is accommodated; a first flange portion which is attached to one end of said box main body, and includes a first cable port through which one of said two cables is received; and a second flange portion which is attached to other end of said box main body, and includes a second cable port through which other of said two cables is received, and a tube portion for retrieving a grounding cable, a main portion of which protrudes inward said box main body.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: May 1, 2007
    Assignees: The Furukawa Electric Co., Ltd., Fujikura Ltd., Viscas Corporation
    Inventors: Yukihiro Yagi, Shozo Kobayashi, Hiroshi Niinobe, Yasuichi Mitsuyama, Noriaki Horiguchi, Masahiro Suetsugu
  • Publication number: 20050221650
    Abstract: A cable connecting structure, which includes a cable accommodating box comprising: a box main body in which a connected portion of two cables is accommodated; a first flange portion which is attached to one end of said box main body, and includes a first cable port through which one of said two cables is received; and a second flange portion which is attached to other end of said box main body, and includes a second cable port through which other of said two cables is received, and a tube portion for retrieving a grounding cable, a main portion of which protrudes inward said box main body.
    Type: Application
    Filed: February 28, 2005
    Publication date: October 6, 2005
    Applicants: THE FURUKAWA ELECTRIC CO., LTD., FUJIKURA LTD., Viscas Corporation
    Inventors: Yukihiro Yagi, Shozo Kobayashi, Hiroshi Niinobe, Yasuichi Mitsuyama, Noriaki Horiguchi, Masahiro Suetsugu
  • Patent number: 6340891
    Abstract: The diagnosis method of deterioration of electric power cable is that which diagnoses the deterioration accurately without a especial effort to reduce the harmonics in an electric power source equipment for test. Loss current component, which is obtained by rejecting the capacitive component of frequency f1 contained in the total current flowing in the insulation of the electric power cable, when superimposing a first voltage V1 of frequency f1 and a second voltage V2 of frequency f2 (V1≧V2) to an electric power cable, is measured. Further the current components and the frequency components contained in the current is investigated. The deterioration diagnosis is implemented by frequency components excepting the frequency f1, f2 and the their harmonic.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: January 22, 2002
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yukihiro Yagi, Hideo Tanaka
  • Patent number: 5506626
    Abstract: A closed-caption decoder which uses separate clock generators to produce the sampling frequencies for the clock run-in signal and the data portion of the closed-caption signal. Each of the clock generators generates its signal from a common 12 MHz reference clock signal. The timing of the sampling clock signal for the closed-caption data is advanced at the start of the sampling interval to reduce the total timing errors in the sampling of the closed-caption data. Additionally, the decoder can adaptively select one of four edges of the clock run-in signal to use as its synchronizing reference. Furthermore, the decoder may be adapted to recognize more than one start byte pattern.
    Type: Grant
    Filed: January 14, 1994
    Date of Patent: April 9, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukihiro Yagi, Masayuki Nakaimuki, Shinichi Takahashi, Jeff M. Huard
  • Patent number: 5483289
    Abstract: A circuit and method of data slicing a television signal comprises: an extractor 2 for extracting a specific component from the television signal of analog form; a slicer 3 for slicing the specific component of the television signal produced by the extractor 2 and converting it to its digital form; a decoder 4 for decoding an output of the slicer 3 for display; an initial value storage 10 for storing an initial value of the slice level; slice level controllers 7 and 8 for varying the initial slice level at a predetermined rate; a signal detector 11 for examining whether or not the digitized specific component from the slicer 3 is a desired multiplex signal; a temporary slice level memory 13 for storing the upper and lower levels of the desired multiplex signal detected by the signal detector 11; a calculator 9 for calculating an optimum value of the slice level from the upper and lower levels of the multiplex signal stored in the temporary slice level memory 13; a slice level storage 6 for storing the optimum
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: January 9, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakazu Urade, Hisao Kobayashi, Yukihiro Yagi, Katsuhiko Hashimoto, Sachiko Nishii
  • Patent number: 5469091
    Abstract: A data slice circuit is provided for slicing the caption data or the likes included in a television signal at an optimum voltage. A product between a clock-run signal sliced by a comparator at a tentative reference voltage and a clock signal which is 16 times the clock-run signal is stored in a shift register as 16 bit information, and out of them, only the 8 bits around its center are taken in a duty-factor check block, thereby judging the suitability of the slice level. Based on the result obtained, the value of the counter is increased or decreased, and it is taken as a renewed reference voltage through a pulse width conversion circuit and an integration circuit. Also with data sliced by a renewed reference voltage, the check is executed similarly, and a slicing action at an optimum level is achieved.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: November 21, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.k
    Inventors: Shinichi Takahashi, Masayuki Nakaimuki, Yukihiro Yagi