Abstract: A non-transitory computer-readable recording medium having stored therein a machine learning program executable by one or more computers, the machine learning program includes: in a quantizing process that reduces a bit width to be used for data expression of a parameter included in a machine-learned model in a neural network including a convolution layer, scaling, based on a result of scaling input data in the convolution layer for each input channel, weight data in the convolution layer for the channel; and quantizing the scaled weight data for each output channel of multi-dimensional output data of the convolution layer.

Abstract: An arithmetic processing device includes: a fixed-point operator that executes an operation on a fixed-point number; a floating-point operator that executes an operation on a floating-point number; a first converter that converts a result of the operation by the floating-point operator to a fixed-point number having a second bit width larger than a first bit width; a statistical information acquirer that acquires statistical information of any of the fixed-point number output by the fixed-point operator and the fixed-point number output by the first converter; and a second converter that converts, to a fixed-point number having the first bit width, the fixed-point number that has been output by the fixed-point operator or by the first converter and of which the statistical information has been acquired.

Abstract: A semiconductor device includes an oscillator that oscillates to generate a clock, a circuit that operates based on the clock generated by the oscillator, a temperature detector that detects the temperature of the circuit, a power detector that acquires, as a monitored power value, power consumed by the circuit, and a frequency controller that controls, when the temperature detected by the temperature detector exceeds a temperature threshold, the frequency of the clock of the oscillator so that the monitored power value matches target power that causes the temperature of the circuit to converge to a temperature higher than the temperature threshold.

Abstract: A selecting method includes obtaining by a computer, for each operation state combination for a processor of which element operation states are changeable, a state information record indicating operation states of the operation state combination; measuring by the computer, for each obtained state information record, a power consumption value and a processing performance value of the processor after the processor is switched to the operation states indicated by the state information record, the power consumption value and the processing performance value being measured by executing a specific program on the processor after the processor is switched to the operation states indicated by the state information record; and selecting by the computer, based on the measured processing performance values and for each predetermined power consumption value, a state information record for which the measured power consumption value is the predetermined power consumption value or less among the obtained state information re

Abstract: An information processing apparatus includes processing devices including: an arithmetic processing circuit for executing arithmetic processing and generating a plurality of event signals corresponding to events executed in the arithmetic processing; a plurality of coefficient value holding circuitry respectively for holding a coefficient value corresponding to any one of events to be executed by the arithmetic processing circuit; an accumulated value holding circuit for holding an accumulated value obtained by using one or more of the coefficient values held by specified coefficient value holding circuitry corresponding to the event signals; a power upper limit holding circuit for holding power upper limits of each processing device which correspond to a power upper limit of the information processing apparatus; and a control circuit for controlling at least one of a voltage and a frequency of each of the processing devices such that the accumulated value does not exceed the power upper limit.

Abstract: A semiconductor device includes: a circuit configured to operate according to a clock; a temperature sensor configured to detect a temperature of the circuit; and a controller configured to control a frequency of the clock based on a temporal difference of power consumption of the circuit when the temperature detected by the temperature sensor exceeds a predetermined value.

Abstract: A selecting method includes obtaining by a computer, for each operation state combination for a processor of which element operation states are changeable, a state information record indicating operation states of the operation state combination; measuring by the computer, for each obtained state information record, a power consumption value and a processing performance value of the processor after the processor is switched to the operation states indicated by the state information record, the power consumption value and the processing performance value being measured by executing a specific program on the processor after the processor is switched to the operation states indicated by the state information record; and selecting by the computer, based on the measured processing performance values and for each predetermined power consumption value, a state information record for which the measured power consumption value is the predetermined power consumption value or less among the obtained state information re

Abstract: A semiconductor device includes: a circuit configured to operate according to a clock; a temperature sensor configured to detect a temperature of the circuit; and a controller configured to control a frequency of the clock based on a temporal difference of power consumption of the circuit when the temperature detected by the temperature sensor exceeds a predetermined value.

Abstract: A method of calculating power consumption of an integrated circuit based on circuit information representing an internal configuration of each circuit and connection-between-circuits information is performed by a computer.

Abstract: Instructions decoded by the instruction decoding part are issued to an arithmetic and logic part, a consumption current value that has been consumed by the arithmetic and logic part with instructions issued during a first predetermined period and a consumption current estimated value for a current that is consumed by the arithmetic and logic part with instructions issuable during a second predetermined period of the decoded instructions are calculated, and issuance of some instructions of the decoded instructions is inhibited in the second predetermined period in a case where a change amount of the consumption current estimated value with respect to the consumption current value exceeds a predetermined limit value.

Abstract: A clock-gating circuit insertion method includes inserting a clock-gating circuit into a position detected on the basis of a circuit data. Timing analysis of an enable signal is performed for the clock-gating circuit. An upper limit of delay variations for the enable signal is calculated to satisfy setup conditions on the basis of the result of the timing analysis. A selector-equipped clock-gating circuit including a selector circuit and a clock-gating circuit is inserted into the candidate position for insertion. The selector circuit selects and outputs the enable signal when delay variations are not above the upper limit. The selector circuit selects and outputs a signal designating the passing of a clock signal when the delay variations are above the upper limit. The clock-gating circuit passes or intercepts the clock signal on the basis of the output signal of the selector circuit.

Abstract: A clock-gating circuit insertion method includes inserting a clock-gating circuit into a position detected on the basis of a circuit data. Timing analysis of an enable signal is performed for the clock-gating circuit. An upper limit of delay variations for the enable signal is calculated to satisfy setup conditions on the basis of the result of the timing analysis. A selector-equipped clock-gating circuit including a selector circuit and a clock-gating circuit is inserted into the candidate position for insertion. The selector circuit selects and outputs the enable signal when delay variations are not above the upper limit. The selector circuit selects and outputs a signal designating the passing of a clock signal when the delay variations are above the upper limit. The clock-gating circuit passes or intercepts the clock signal on the basis of the output signal of the selector circuit.

Abstract: An output circuit including: a tri-state output circuit capable of outputting high-impedance state, high-level state, and low-level state, in which the high-level state and low-level state are low-impedance state, and switching the high-impedance state and the low-impedance state in accordance with a first control signal; and a delay circuit outputting the first control signal to the tri-state output circuit by inputting a second control signal and delaying the second control signal so that timing delay time of the second control signal switching the high-impedance state to the low-impedance state is longer than the timing delay time of the second control signal switching the low-impedance state to the high-impedance state, is provided.