Patents by Inventor Yukiji Hashimoto

Yukiji Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and semiconductor device layout designing method
    Patent number: 8028264
    Abstract: A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: September 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Junichi Shimada, Fumihiro Kimura, Yoichi Matsumura, Takako Ohashi, Nobuyuki Iwauchi, Takeya Fujino, Takayuki Araki, Yukiji Hashimoto, Takuya Yasui, Hirofumi Taguchi
  • Interconnect structure of semiconductor integrated circuit, and design method and device therefor
    Patent number: 7913221
    Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Hirofumi Miyashita, Chie Kabuo, Nobuyuki Iwauchi, Yoichi Matsumura, Fumihiro Kimura, Tatsuo Gou, Yukiji Hashimoto
  • Interconnect structure of semiconductor integrated circuit, and design method and device therefor
    Publication number: 20080097641
    Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
    Type: Application
    Filed: October 19, 2007
    Publication date: April 24, 2008
    Inventors: Hirofumi Miyashita, Chie Kabuo, Nobuyuki Iwauchi, Yoichi Matsumura, Fumihiro Kimura, Tatsuo Gou, Yukiji Hashimoto
  • Semiconductor device and semiconductor device layout designing method
    Publication number: 20070252258
    Abstract: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventors: Junichi Shimada, Fumihiro Kimura, Yoichi Matsumura, Takako Ohashi, Nobuyuki Iwauchi, Takeya Fujino, Takayuki Araki, Yukiji Hashimoto, Takuya Yasui, Hirofumi Taguchi