Patents by Inventor Yukiko Nakaoka

Yukiko Nakaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and manufacturing method thereof
    Patent number: 6815255
    Abstract: A semiconductor device includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The first and the second semiconductor chips are integrated so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip is polished from the opposite side of the second main surface so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: November 9, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao, Hiroaki Fujimoto
  • Semiconductor device and manufacturing method thereof
    Publication number: 20040029314
    Abstract: A semiconductor device includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The first and the second semiconductor chips are integrated so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip is polished from the opposite side of the second main surface so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip.
    Type: Application
    Filed: July 18, 2003
    Publication date: February 12, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao, Hiroaki Fujimoto
  • Semiconductor device and method for fabricating the same
    Publication number: 20030127722
    Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.
    Type: Application
    Filed: February 24, 2003
    Publication date: July 10, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao
  • Semiconductor device and method for fabricating the same
    Patent number: 6583512
    Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: June 24, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao
  • Semiconductor device and method for fabricating the same
    Patent number: 6558977
    Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: May 6, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao
  • Semiconductor device and manufacturing method thereof
    Publication number: 20030032216
    Abstract: A semiconductor device includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The first and the second semiconductor chips are integrated so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip is polished from the opposite side of the second main surface so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip.
    Type: Application
    Filed: February 5, 2002
    Publication date: February 13, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao, Hiroaki Fujimoto
  • Semiconductor device and method for fabricating the same
    Publication number: 20020079590
    Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.
    Type: Application
    Filed: October 1, 2001
    Publication date: June 27, 2002
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao