Patents by Inventor Yukimasa Satou

Yukimasa Satou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5459338
    Abstract: A gate turn-off thyristor having a p-emitter layer in the anode side, an n-base layer, a p-base layer and an n-emitter layer in the cathode side. The n-base layer is composed of a first layer portion adjacent to the p-emitter layer, a second layer portion adjacent to the p-base layer and having a lower impurity concentration than the first layer portion, and is constituted by a structure which alters a travelling path of positive holes injected from the p-emitter layer.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: October 17, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Takayanagi, Susumu Murakami, Yukimasa Satou, Satoshi Matsuyoshi, Yasuhiro Mochizuki, Hidekatsu Onose
  • Patent number: 5430311
    Abstract: A constant-voltage diode has a first semiconductor region of a first conductivity type, an adjoining semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type adjoining the second semiconductor region, and a fourth semiconductor region of the first conductivity type partially surrounded by the second semiconductor region. At low reverse biases between a cathode electrode and an anode electrode, the behavior of the device is determined by the pn junction between the first and second semiconductor regions. As the reverse biasing increases, the depletion layers of that junction will reach the fourth semiconductor region, but the reverse bias at this time is insufficient to break down that junction. A further increase of reverse bias causes breakdown of the pn junction between the third and fourth semiconductor regions. This effect is achieved by suitable impurity concentrations in the semiconductor regions.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: July 4, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Murakami, Yukimasa Satou, Hiroshi Narita
  • Patent number: 5324967
    Abstract: In a turn off type semiconductor device, an n-type emitter layer is divided into a plurality of elements by trenches. A silicide layer of a high melting point metal is provided on a p-type layer adjacent to the individual elements of the n-type emitter layer on a bottom of each of the trenches. A gate electrode is provided on the associated silicide layer so as to surround the plurality of elements of the n-type emitter layer obtained by the division of the emitter layer. An insulator is filled in each of the trenches dividing the n-type emitter layer surrounded by the gate electrode. A cathode electrode is provided on both the insulators and the n-type emitter layer.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: June 28, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Honma, Yukimasa Satou, Susumu Murakami, Tsutomu Yatsuo, Isamu Sanpei, Kenji Yagishita
  • Patent number: 5021855
    Abstract: A gate turn-off thyristor includes a cathode emitter of n-type, a cathode base of p-type, an anode base of n-type and an anode emitter of p-type. A gate electrode is electrically connected to the p cathode base to enclose and define an elemental gate turn-off thyristor region. A plurality of n cathode emitter regions are arranged in proximity to each other in the elemental gate turn-off thyristor region. A highly-doped buried gate region is provided in the p cathode base with the substantially identical configuration for each n cathode emitter regions.
    Type: Grant
    Filed: March 20, 1989
    Date of Patent: June 4, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Saburo Oikawa, Tsutomu Yatsuo, Yukimasa Satou
  • Patent number: 4825270
    Abstract: The present invention relates to a buried gate type gate turn-off thyristor. A low-resistance layer which is buried in a cathode base layer has a multiplicity of small bores below a cathode emitter layer. The distance between each pair of adjacent small bores and the thickness of the low-resistance layer are each set so as to be smaller than the carrier diffusion length in an anode base layer. In an on-state, carries flow through the low-resistance layer, thereby allowing the low-resistance layer to become conductive, and thus lowering the on-state voltage. A reduction in the dimension of the small bores lowers the resistance of the low-resistance layer and hence lowers the gate drawing out resistance, so that the interrupting capacity is improved.
    Type: Grant
    Filed: February 2, 1987
    Date of Patent: April 25, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yukimasa Satou, Tsutomu Yatsuo, Saburo Oikawa, Isamu Sanpei