Abstract: A three-dimensional position and posture recognition device speeds estimation of a position posture and a gripping coordinate posture of a gripping target product. The device includes: a sensor unit configured to measure a distance between an image of an object and the object; and a processing unit configured to calculate an object type included in the image, read model data of each object from the external memory, and create structured model data having a resolution set for each object from the model data, generate measurement point cloud data of a plurality of resolutions from information on a distance between an image of the object and the object, perform a K neighborhood point search using the structured model data and the measurement point cloud data, and perform three-dimensional position recognition processing of the object by rotation and translation estimation regarding a point obtained from the K neighborhood point search.

Abstract: A three-dimensional position and posture recognition device speeds estimation of a position posture and a gripping coordinate posture of a gripping target product. The device includes: a sensor unit configured to measure a distance between an image of an object and the object; and a processing unit configured to calculate an object type included in the image, read model data of each object from the external memory, and create structured model data having a resolution set for each object from the model data, generate measurement point cloud data of a plurality of resolutions from information on a distance between an image of the object and the object, perform a K neighborhood point search using the structured model data and the measurement point cloud data, and perform three-dimensional position recognition processing of the object by rotation and translation estimation regarding a point obtained from the K neighborhood point search.

Abstract: The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Abstract: The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Abstract: The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.

Abstract: In a transmission portion of a semiconductor device, a first amplification portion receives a digital baseband signal and amplifies the signal with a first gain through digital processing. A digital-to-analog conversion portion converts the digital baseband signal amplified by the first amplification portion into an analog baseband signal. A modulation portion generates a transmission signal by modulating a local oscillation signal with the analog baseband signal. A second amplification portion amplifies the transmission signal with a variable second gain. A control unit receives information representing a transmission mode and adjusts the first gain in accordance with the transmission mode.

Abstract: The semiconductor integrated communication circuit includes: a low-noise amplifier; a receive mixer; a receive VCO; a demodulation-processing circuit; a modulation-processing circuit; a transmit mixer; a transmit VCO; a second-order-distortion-characteristic-calibration circuit; a quadrature-receive-signal-calibration circuit; and a test-signal generator. The test-signal generator generates first and second test signals using the transmit VCO. In the second-order-distortion-characteristic-calibration mode, the second-order-distortion-characteristic-calibration circuit variably changes an operation parameter of the receive mixer thereby to calibrate the second-order distortion characteristic to achieve its best condition while the first test signal is supplied to the receive mixer.

Abstract: A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: This invention provides a wireless transmitter circuit for mobile communication apparatus and this circuit can be configured with fewer components and is suitable for downsizing. A single PLL synthesizer serves as both RF frequency band PLL and IF frequency band PLL among three oscillators for TX, RX and IF frequency bands, which have been required in conventional mobile communication apparatus. The number of necessary oscillators occupying a large area within a chip is reduced and the number of components is decreased. Specifically, circuitry is arranged to generate local oscillation signals for RF and IF frequency bands by frequency dividing the output of a VCO of the RF frequency band PLL.

Abstract: A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block.

Abstract: When generating an RF test signal for mismatch calibration for receiver in order to calibrate reception mismatch of an I-phase signal and a Q-phase signal that are output from demodulated signal processing circuits coupled to mixers for receiving, a Tx VCO avoids covering the higher frequency of an RF received signal in an FDD system. An RF test signal generating unit generates, in a calibration mode of a mismatch calibration for receiver circuit, the RF test signal by using an oscillation output signal of the Tx VCO and other circuits, and supplies the same to the mixers for receiving via a switch. The RF test signal has a frequency within an RF reception frequency band that is higher than that of an RF transmission signal with the maximum frequency band of multiband radio frequency communications. By switching the switch in a reception mode, an output of a low-noise amplifier that amplifies the RF received signal received by an antenna is supplied to each of the mixers for receiving.

Abstract: The semiconductor integrated communication circuit includes: a low-noise amplifier; a receive mixer; a receive VCO; a demodulation-processing circuit; a modulation-processing circuit; a transmit mixer; a transmit VCO; a second-order-distortion-characteristic-calibration circuit; a quadrature-receive-signal-calibration circuit; and a test-signal generator. The test-signal generator generates first and second test signals using the transmit VCO. In the second-order-distortion-characteristic-calibration mode, the second-order-distortion-characteristic-calibration circuit variably changes an operation parameter of the receive mixer thereby to calibrate the second-order distortion characteristic to achieve its best condition while the first test signal is supplied to the receive mixer.

Abstract: The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.