Abstract: A dynamic random access memory device is responsive to a row address signal and a column address signal supplied in synchronism with a system clock signal for providing a data path from a data input/output port and a memory cell selected from the memory cell array, and latch circuits are provided in the addressing section and the data transferring path for temporarily storing address decoded signal and write-in and read-out data bits in response to latch control signals higher in frequency than the system clock signal, thereby controlling the data stream in a pipeline fashion.

Abstract: A data output circuit with a first and a second input node and an output node has a two-input NAND gate connected to the two input nodes, a two-input NOR gate connected to the two input nodes and a first to a fourth field effect transistor. The first and second transistors are connected in parallel between a power source line and the output node with the gate of the first transistor being connected to an output of the NAND gate and with the gate of the second transistor being connected to the first input node. The third and fourth transistors are connected in parallel between the output node and the ground line with the gate of the third transistor being connected to an output of the NOR gate and with the gate of the fourth transistor being connected to the first input node. The first and second transistors are P-channel MOS transistors and the second and third transistors are N-channel MOS transistors.

Abstract: An improved integrated circuit provided with a reduced capacitance of common external terminal connected to a plurality of circuits is disclosed. A switch is inserted between the external terminal and at least one of the circuits. The switch is controlled in such manner that it is rendered conductive when that circuit is to receive the signal at the external terminal and non-conductive when the circuit is not to receive the signal at the external terminal therein.

Abstract: An improved active pull-up circuit which can be fabricated with reduced number of elements and operate with a small power consumption.A first switch is provided between a refresh voltage terminal and a true circuit node to be pulled-up. A second switch controlled by a potential of a complementary circuit node is provided for operatively discharging the charge of a control electrode of the first switch. A pull-up clock is applied via a capacitor to the control electrode of the first switch.

Abstract: A timing signal generator which can operate stably even when, or directly after, a power supply is switched on. The generator is of the type having a first dynamic delay circuit for generating a first timing signal in response to said input control signal and a second dynamic delay circuit for generating a second timing signal in response to the first timing signal, and is featured by a first transistor connected between the output of the first dynamic delay circuit and a voltage terminal with a gate connected to the input of the first dynamic delay circuit and a second transistor connected to the output of the second dynamic delay circuit and the voltage terminal with a gate connected to receive the first timing signal.