Patents by Inventor Yukio Shimizu
Yukio Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146806Abstract: An intermediate device 10A includes a transfer unit 11 that transfers a request including data to be transmitted from a local 30 to a remote 50, and a generation unit 12 that generates a pseudo-response to the request and returns the pseudo-response to the local 30. The intermediate device 10B includes a discard unit 13 that discards a response to the request from the remote 50. An intermediate device 20B includes a generation unit 22 that generates a pseudo-request based on an initial request for requesting data transmission from the local 30 to the remote 50 and transmits the pseudo-request to the remote 50, and a transfer unit 24 that transfers a response including data to be transmitted from the remote 50 to the local 30. The intermediate device 20A includes the discard unit 21 that discards a subsequent request from the local 30.Type: ApplicationFiled: June 10, 2021Publication date: May 2, 2024Inventors: Junki ICHIKAWA, Hideki NISHIZAWA, Kenji SHIMIZU, Yukio TSUKISHIMA, Toru MANO, Tomoya HIBI, Kiwami INOUE
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Publication number: 20240072119Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, a first member, a first layer, and a second layer. The silicon carbide member includes a first region. The first member includes silicon and oxygen. The first layer is provided between the first region and the first member. The first layer includes a bond between silicon and nitrogen. The second layer is provided between the first layer and the first member. The second layer includes a bond between silicon and oxygen and a bond between silicon and nitrogen.Type: ApplicationFiled: February 16, 2023Publication date: February 29, 2024Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio NAKABAYASHI, Tatsuo SHIMIZU, Toshihide ITO, Chiharu OTA, Johji NISHIO
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Patent number: 11579497Abstract: A substrate for a display includes a substrate section on which a flexible substrate and a driver are mounted, a flexible substrate side terminal area, disposed in a mounting area on the substrate section for the flexible substrate, to which a signal is inputted from the flexible substrate, a driver side terminal area, disposed in a mounting area on the substrate section for the driver, through which at least a part of the signal is inputted and outputted to the driver, a wire, disposed to extend from the mounting area on the substrate section for the flexible substrate to the mounting area for the driver and connected to the flexible substrate side terminal area and the driver side terminal area, through which the signal is transmitted, and a shield section, disposed to overlap the wire via an insulating film on the substrate section, that is kept at a constant potential.Type: GrantFiled: January 22, 2021Date of Patent: February 14, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Yukio Shimizu, Shinzoh Murakami
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Publication number: 20210247641Abstract: A substrate for a display includes a substrate section on which a flexible substrate and a driver are mounted, a flexible substrate side terminal area, disposed in a mounting area on the substrate section for the flexible substrate, to which a signal is inputted from the flexible substrate, a driver side terminal area, disposed in a mounting area on the substrate section for the driver, through which at least a part of the signal is inputted and outputted to the driver, a wire, disposed to extend from the mounting area on the substrate section for the flexible substrate to the mounting area for the driver and connected to the flexible substrate side terminal area and the driver side terminal area, through which the signal is transmitted, and a shield section, disposed to overlap the wire via an insulating film on the substrate section, that is kept at a constant potential.Type: ApplicationFiled: January 22, 2021Publication date: August 12, 2021Inventors: YUKIO SHIMIZU, SHINZOH MURAKAMI
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Patent number: 10866472Abstract: An array substrate includes at least: a glass substrate on which a driver is mounted; a panel side output terminal disposed in a mounting area of the glass substrate and connected to the driver; a first terminal portion; a gate insulation film including a first contact hole at a position overlapping a first terminal portion; a second terminal portion disposed to overlap at least a first contact hole and an opening edge of the first contact hole; a first interlayer insulation film including a second contact hole at a position overlapping a second terminal portion not to overlap the first contact hole; and a third terminal portion disposed to overlap at least the second contact hole and an opening edge of the second contact hole.Type: GrantFiled: September 7, 2017Date of Patent: December 15, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Yukio Shimizu, Shinzoh Murakami, Takeshi Horiguchi
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Patent number: 10818626Abstract: Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.Type: GrantFiled: November 24, 2017Date of Patent: October 27, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Seiji Muraoka, Yukio Shimizu, Motoji Shiota
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Patent number: 10811488Abstract: A display device includes a TFT layer provided in a display area, a bending section and a terminal in a non-active area, and a terminal wiring line that connects to the terminal through the bending section, and the terminal wiring line includes a first wiring line and a second wiring line each positioned on both sides of the bending section and a third wiring line that passes through the bending section and is electrically connected with each of the first wiring line and the second wiring line and curved so as to have recesses and protrusions.Type: GrantFiled: September 22, 2017Date of Patent: October 20, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Takashi Matsui, Yukio Shimizu, Gen Nagaoka, Motoji Shiota
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Publication number: 20190363153Abstract: A display device includes a TFT layer provided in a display area, a bending section and a terminal in a non-active area, and a terminal wiring line that connects to the terminal through the bending section, and the terminal wiring line includes a first wiring line and a second wiring line each positioned on both sides of the bending section and a third wiring line that passes through the bending section and is electrically connected with each of the first wiring line and the second wiring line and curved so as to have recesses and protrusions.Type: ApplicationFiled: September 22, 2017Publication date: November 28, 2019Inventors: Takashi MATSUI, Yukio SHIMIZU, Gen NAGAOKA, Motoji SHIOTA
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Publication number: 20190295974Abstract: Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.Type: ApplicationFiled: November 24, 2017Publication date: September 26, 2019Applicant: SHARP KABUSHIKI KAISHAInventors: SEIJI MURAOKA, YUKIO SHIMIZU, MOTOJI SHIOTA
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Publication number: 20190204655Abstract: An array substrate includes at least: a glass substrate on which a driver is mounted; a panel side output terminal disposed in a mounting area of the glass substrate and connected to the driver; a first terminal portion; a gate insulation film including a first contact hole at a position overlapping a first terminal portion; a second terminal portion disposed to overlap at least a first contact hole and an opening edge of the first contact hole; a first interlayer insulation film including a second contact hole at a position overlapping a second terminal portion not to overlap the first contact hole; and a third terminal portion disposed to overlap at least the second contact hole and an opening edge of the second contact hole.Type: ApplicationFiled: September 7, 2017Publication date: July 4, 2019Inventors: YUKIO SHIMIZU, SHINZOH MURAKAMI, TAKESHI HORIGUCHI
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Publication number: 20190041685Abstract: The semiconductor device of the present invention includes: a first bump group including multiple first bumps aligned in a long side direction; a second bump group including multiple second bumps aligned in the long side direction; and a third bump group including multiple third bumps between the first bump group and the second bump group, wherein on the surface to be connected to the display device, in a short side direction perpendicular to the long side direction, no second bump is disposed or at least one of the multiple second bumps is disposed at least one of positions facing the multiple third bumps, the at least one of the multiple second bumps being a dummy bump.Type: ApplicationFiled: February 3, 2017Publication date: February 7, 2019Applicant: SHARP KABUSHIKI KAISHAInventors: SHINZOH MURAKAMI, YUKIO SHIMIZU, TAKESHI HORIGUCHI
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Publication number: 20190033646Abstract: A terminal connection structure includes a large panel-side terminal (a high resistance terminal) 28 having relatively high electric resistance, and a large flexible board-side terminal (a low resistance terminal) 30 having relatively low electric resistance and connected to the large panel-side terminal 28. The large flexible board-side terminal 30 includes separated large flexible board-side terminals (separated low resistance terminals) 30a that are arranged at intervals and have a width relatively larger in a distal end side portion 30a2 with respect to a basal end side portion 30a1.Type: ApplicationFiled: January 20, 2017Publication date: January 31, 2019Applicant: Sharp Kabushiki KaishaInventors: Yukio SHIMIZU, Motoji SHIOTA, Keiji AOTA
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Patent number: 9659880Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on an upper surface of a wiring substrate, and a magnetic shield arranged above the upper surface of the wiring substrate to cover an upper side of the semiconductor element. The magnetic shield is formed from a soft magnetic material and includes inclined faces that are inclined straight with respect to the upper surface of the wiring substrate at a portion overlapped with the semiconductor element in a plan view.Type: GrantFiled: March 3, 2016Date of Patent: May 23, 2017Assignee: Shinko Electric Industries Co., LTD.Inventors: Manabu Nakamura, Yukio Shimizu, Nahomi Inoue
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Publication number: 20160268215Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on an upper surface of a wiring substrate, and a magnetic shield arranged above the upper surface of the wiring substrate to cover an upper side of the semiconductor element. The magnetic shield is formed from a soft magnetic material and includes inclined faces that are inclined straight with respect to the upper surface of the wiring substrate at a portion overlapped with the semiconductor element in a plan view.Type: ApplicationFiled: March 3, 2016Publication date: September 15, 2016Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: MANABU NAKAMURA, YUKIO SHIMIZU, NAHOMI INOUE
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Patent number: 9217888Abstract: A liquid crystal display device includes: a liquid crystal panel having a display area and non-display area; a flexible substrate in the non-display area and connected to a control circuit substrate; a plurality of drivers in the non-display area; a plurality of connection wiring lines in the non-display area for connecting the flexible substrate to the plurality of drivers; a first driver; a second driver that is arranged further away from the flexible substrate than the first driver; a non-overlapping connection wiring line that connects the second driver to the flexible substrate and that does not overlap the first driver; and an overlapping connection wiring line that connects the second driver to the flexible substrate and that has a least a portion thereof overlapping the first driver.Type: GrantFiled: April 19, 2013Date of Patent: December 22, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Yukio Shimizu, Seiji Muraoka, Motoji Shiota, Takeshi Horiguchi
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Patent number: 9207477Abstract: A display module 1 of the present invention includes a first board 3, a second board 4, a base film 5, and a circuit member 2. The first board 3 and the second board 4 are bonded together to face with each other. The base film 5 is provided between the first board 3 and the second board 4 and extends outwardly from an end of the first board 3. The base film 5 has an insulating property and the extended portion is bent to an outer surface side of one of the first board 3 and the second board 4. The circuit member 2 is formed on the base film 5.Type: GrantFiled: April 23, 2012Date of Patent: December 8, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroki Miyazaki, Motoji Shiota, Takatoshi Kira, Gen Nagaoka, Seiji Muraoka, Makoto Tamaki, Keiji Aota, Yukio Shimizu, Takashi Matsui, Hiroki Nakahama, Hiroki Makino, Minoru Horino
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Publication number: 20150319849Abstract: The present invention provides a component securing structure that forms a wiring unit on a TFT glass substrate that is capable of transmitting UV light. A component, such as a driver IC and/or an FPC, is electrically connected to the wiring unit and is secured to the TFT glass substrate by a UV-curable ACF. An opening for transmitting UV light is formed in a light shielding layer of the wiring unit. UV light irradiated from the back side of the TFT glass substrate passes through the opening and directly irradiates the UV-curable ACF.Type: ApplicationFiled: December 9, 2013Publication date: November 5, 2015Applicant: SHARP KABUSHIKI KAISHAInventors: Yukio SHIMIZU, Motoji SHIOTA, Hiroki MIYAZAKI, Hiroki NAKAHAMA, Seiji MURAOKA, Takeshi HORIGUCHI
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Patent number: 9117048Abstract: A layout pattern generating apparatus and a layout pattern generating method for an element used for layout design of a semiconductor integrated circuit (LSI) provide a reduction in time for generating a layout pattern with high versatility. The layout pattern generating apparatus for generating a layout pattern of each of elements included in a semiconductor integrated circuit, includes, for example, a storage, a basic figure generator, an additional figure generator, a display unit and an operation input unit. The apparatus and method also utilize at least terminal figure relative position information, figure adjustment value information, and additional figure relative position information, the additional figure being a figure other than the basic figure. The basic figure generator generates the effective area figure and the terminal figure of the layout pattern generation target element, and the additional figure generator generates the additional figure of the layout pattern generation target element.Type: GrantFiled: June 16, 2011Date of Patent: August 25, 2015Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Yukio Shimizu
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Publication number: 20150109550Abstract: A liquid crystal display device includes: a liquid crystal panel having a display area and non-display area; a flexible substrate (13) in the non-display area and connected to a control circuit substrate; a plurality of drivers (21) in the non-display area; a plurality of connection wiring lines (27) in the non-display area for connecting the flexible substrate to the plurality of drivers; a first driver (21A); a second driver (21B) that is arranged further away from the flexible substrate than the first driver; a non-overlapping connection wiring line (32) that connects the second driver to the flexible substrate and that does not overlap the first driver; and an overlapping connection wiring line (31) that connects the second driver to the flexible substrate and that has a least a portion thereof overlapping the first driver.Type: ApplicationFiled: April 19, 2013Publication date: April 23, 2015Applicant: Sharp Kabushiki KaishaInventors: Yukio Shimizu, Seiji Muraoka, Motoji Shiota, Takeshi Horiguchi
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Publication number: 20140092338Abstract: A display module 1 of the present invention includes a first board 3, a second board 4, a base film 5, and a circuit member 2. The first board 3 and the second board 4 are bonded together to face with each other. The base film 5 is provided between the first board 3 and the second board 4 and extends outwardly from an end of the first board 3. The base film 5 has an insulating property and the extended portion is bent to an outer surface side of one of the first board 3 and the second board 4. The circuit member 2 is formed on the base film 5.Type: ApplicationFiled: April 23, 2012Publication date: April 3, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Hiroki Miyazaki, Motoji Shiota, Takatoshi Kira, Gen Nagaoka, Seiji Muraoka, Makoto Tamaki, Keiji Aota, Yukio Shimizu, Takashi Matsui, Hiroki Nakahama, Hiroki Makino, Minoru Horino