Patents by Inventor Yukio Takigawa
Yukio Takigawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8675808Abstract: A natural-circulation type boiling water reactor includes a plurality of divided chimneys provided above a reactor core and a number of fuel assemblies are charged in the reactor core. The natural-circulation type boiling water reactor is provided with a pressure equalization structure arranged on rectangular-columnar lattice plates of the divided chimneys for equalizing pressures in divided chimney portions so as to equalize the pressures of the divided chimneys with the pressure equalization structure.Type: GrantFiled: August 11, 2006Date of Patent: March 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Nobuaki Abe, Yutaka Takeuchi, Yukio Takigawa, Mikihide Nakamaru
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Patent number: 7811936Abstract: A method produces a semiconductor device having an interconnection structure disposed above a substrate, wherein the interconnection structure has an interconnection and an insulator layer including a low-permittivity layer. The method includes an etching step forming openings in the insulator layer to expose a surface of the interconnection by dry etching, a cleaning step cleaning the surface of the interconnection and the openings in the insulator layer, and a forming step forming another interconnection by filling a conductor material into the openings. The cleaning step includes a first cleaning process using a cleaning liquid, a rinsing process using a rinsing liquid including water and carbonic acid or organic acid, and a second cleaning process using a neutral or alkaline hydrogen aqueous solution that is supplied to the surface of the interconnection and the openings in the insulator layer.Type: GrantFiled: January 31, 2008Date of Patent: October 12, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Yukio Takigawa
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Patent number: 7709394Abstract: A method for processing a substrate having an insulation film and a metal layer thereon comprises the steps of supplying a carboxylic acid anhydride to the substrate, and heating the substrate during the step of supplying the carboxylic acid anhydride to the substrate.Type: GrantFiled: March 19, 2007Date of Patent: May 4, 2010Assignees: Tokyo Electron Limited, Fujitsu Limited, Ebara CorporationInventors: Hidenori Miyoshi, Kenji Ishikawa, Yukio Takigawa, Yoshihiro Nakata, Hideki Tateishi
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Publication number: 20100007020Abstract: A semiconductor device includes: an insulating film including a porous insulating material and formed above a substrate; an interconnection wire including copper and buried in a groove formed at least in an obverse surface of the insulating film; and a barrier insulating film including an insulating material containing a nitrogen heterocyclic compound and formed over the insulating film and the interconnection wire.Type: ApplicationFiled: June 30, 2009Publication date: January 14, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Yukio Takigawa
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Publication number: 20090116608Abstract: A natural-circulation type boiling water reactor according to the present invention includes a plurality of divided chimneys provided above a reactor core and a number of fuel assemblies are charged in the reactor core. The natural-circulation type boiling water reactor is provided with a pressure equalization structure arranged on rectangular-columnar lattice plates of the divided chimneys at an outlet of the reactor core for equalizing pressures in divided chimney portions so as to equalize the pressures of the divided chimneys with the pressure equalization structure.Type: ApplicationFiled: August 11, 2006Publication date: May 7, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nobuaki Abe, Yutaka Takeuchi, Yukio Takigawa, Mikihide Nakamaru
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Patent number: 7481264Abstract: A steam condenser which condenses steam exhausted from a steam turbine. Heat transfer tubes are arrayed below the steam turbine inside the container. Cooling medium flows inside the heat transfer tubes. The heat transfer tubes extend horizontally, and include at least two upper heat transfer tube groups and at least two lower heat transfer tube groups arranged with a gap between each other. Each heat transfer tube group is constituted by arraying heat transfer tubes like a grid. At a lower part between the lower heat transfer tube groups, a baffle plate which obstructs flow of steam extends horizontally. Between the upper and lower heat transfer tube groups, inter-tube-group inundation prevention plates extend horizontally. In each heat transfer tube group, an enclosure part extends to guide gas from the enclosure part to outside of the container through a gas extraction duct.Type: GrantFiled: May 27, 2005Date of Patent: January 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshihiro Yoshii, Shunichi Goshima, Yukio Takigawa, Tomoko Nakajima, legal representative, Yuuichi Nakajima, legal representative, Miyuki Nakajima, legal representative, Fumio Obara, Akira Nemoto, Shunji Kawano, Yuji Inoue, Shoji Nakajima
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Publication number: 20080166872Abstract: A method produces a semiconductor device having an interconnection structure disposed above a substrate, wherein the interconnection structure has an interconnection and an insulator layer including a low-permittivity layer. The method includes an etching step forming openings in the insulator layer to expose a surface of the interconnection by dry etching, a cleaning step cleaning the surface of the interconnection and the openings in the insulator layer, and a forming step forming another interconnection by filling a conductor material into the openings. The cleaning step includes a first cleaning process using a cleaning liquid, a rinsing process using a rinsing liquid including water and carbonic acid or organic acid, and a second cleaning process using a neutral or alkaline hydrogen aqueous solution that is supplied to the surface of the interconnection and the openings in the insulator layer.Type: ApplicationFiled: January 31, 2008Publication date: July 10, 2008Applicant: FUJITSU LIMITEDInventor: Yukio Takigawa
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Patent number: 7390741Abstract: A method for fabricating a semiconductor device comprises the steps of: forming interconnection grooves 38 in an inter-layer insulation film 34; forming an interconnection layer 44 of Cu as the main material in the interconnection grooves 38; and concurrently injecting nitrogen gas and water to the surface of the interconnection layer 44 buried in the interconnection groove 38.Type: GrantFiled: April 5, 2004Date of Patent: June 24, 2008Assignee: Fujitsu LimitedInventors: Yukio Takigawa, Tamotsu Yamamoto, Yoshiyuki Okura, Takahiro Kono, Tsutomu Hosoda
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Publication number: 20070224725Abstract: A method for processing a substrate having an insulation film and a metal layer thereon comprises the steps of supplying a carboxylic acid anhydride to the substrate, and heating the substrate during the step of supplying the carboxylic acid anhydride to the substrate.Type: ApplicationFiled: March 19, 2007Publication date: September 27, 2007Applicants: TOKYO ELECTRON LIMITED, FUJITSU LIMITED, EBARA CORPORATIONInventors: Hidenori MIYOSHI, Kenji Ishikawa, Yukio Takigawa, Yoshihiro Nakata, Hideki Tateishi
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Publication number: 20070148953Abstract: The method comprises the step of forming an interconnection trench 38 in an inter-layer insulation film 34, the step of forming an interconnection layer 44 of Cu as the main material in the interconnection trench 38, and the step of performing nitrogen-two-fluid processing of concurrently spraying pure water with ammonia and hydrogen solved in and nitrogen gas on the surface of the interconnection layer 44 buried in the interconnection trench 38.Type: ApplicationFiled: June 20, 2006Publication date: June 28, 2007Applicant: FUJITSU LIMITEDInventors: Tsukasa Itani, Makoto Sasaki, Yukio Takigawa
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Patent number: 7211519Abstract: After an SiC film (4), an SiO2 film (5) and a silicon nitride film (6) are formed sequentially on an organic low dielectric constant film (3), by performing O2 plasma processing to a surface of the silicon nitride film (6), an oxide layer (7) is formed on the surface of the silicon nitride film (6). Then, a wiring trench pattern is formed on the silicon nitride film (6) and the oxide layer (7), and a resin layer (10) on which a via hole pattern is formed is formed. Subsequently, a portion of the oxide layer (7) exposed from the resin layer (10) is removed along with unnecessary particles.Type: GrantFiled: March 31, 2005Date of Patent: May 1, 2007Assignee: Fujitsu LimitedInventors: Yukio Takigawa, Noriyoshi Shimizu, Toshiya Suzuki, Hajime Kawabe
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Publication number: 20060032618Abstract: A steam condenser which condenses steam exhausted from a steam turbine. Heat transfer tubes are arrayed below the steam turbine inside the container. Cooling medium flows inside the heat transfer tubes. The heat transfer tubes extend horizontally, and include at least two upper heat transfer tube groups and at least two lower heat transfer tube groups arranged with a gap between each other. Each heat transfer tube group is constituted by arraying heat transfer tubes like a grid. At a lower part between the lower heat transfer tube groups, a baffle plate which obstructs flow of steam extends horizontally. Between the upper and lower heat transfer tube groups, inter-tube-group inundation prevention plates extend horizontally. In each heat transfer tube group, an enclosure part extends to guide gas from the enclosure part to outside of the container through a gas extraction duct.Type: ApplicationFiled: May 27, 2005Publication date: February 16, 2006Inventors: Toshihiro Yoshii, Shunichi Goshima, Yukio Takigawa, Shoji Nakajima, Tomoko Nakajima, Yuuichi Nakajima, Miyuki Nakajima, Fumio Obara, Shunji Kawano, Akira Nemoto, Yuji Inoue
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Patent number: 6943115Abstract: A method is provided for manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a set of conducting portions which are electrically connected to each other to have a surface area of no less than 500 ?m2 and which include a wiring having a width of no more than 1.0 ?m. The method includes a polishing step for flattening the conducting portions together with the insulating film by chemical mechanical polishing, a chemical cleaning step for cleaning the flattened surface of the insulating film with a cleaning liquid, and a rising step for removing the cleaning liquid using a rinsing liquid. The rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.Type: GrantFiled: December 23, 2002Date of Patent: September 13, 2005Assignee: Fujitsu LimitedInventors: Hiroshi Horiuchi, Tamotsu Yamamoto, Yukio Takigawa, Shigeru Suzuki, Nobuaki Santo, Motoshu Miyajima
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Publication number: 20050191852Abstract: After an SiC film (4), an SiO2 film (5) and a silicon nitride film (6) are formed sequentially on an organic low dielectric constant film (3), by performing O2 plasma processing to a surface of the silicon nitride film (6), an oxide layer (7) is formed on the surface of the silicon nitride film (6). Then, a wiring trench pattern is formed on the silicon nitride film (6) and the oxide layer (7), and a resin layer (10) on which a via hole pattern is formed is formed. Subsequently, a portion of the oxide layer (7) exposed from the resin layer (10) is removed along with unnecessary particles.Type: ApplicationFiled: March 31, 2005Publication date: September 1, 2005Applicant: FUJITSU LIMITEDInventors: Yukio Takigawa, Noriyoshi Shimizu, Toshiya Suzuki, Hajime Kawabe
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Publication number: 20050136661Abstract: A method for fabricating a semiconductor device comprises the steps of: forming interconnection grooves 38 in an inter-layer insulation film 34; forming an interconnection layer 44 of Cu as the main material in the interconnection grooves 38; and concurrently injecting nitrogen gas and water to the surface of the interconnection layer 44 buried in the interconnection groove 38.Type: ApplicationFiled: April 5, 2004Publication date: June 23, 2005Applicant: FUJITSU LIMITEDInventors: Yukio Takigawa, Tamotsu Yamamoto, Yoshiyuki Okura, Takahiro Kono, Tsutomu Hosoda
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Patent number: 6693046Abstract: A method of manufacturing a semiconductor device includes the steps of: (X) forming a first hydrophobic insulating layer above a semiconductor substrate; (Y) hydrophilizing a surface of the first hydrophobic insulating layer; and (Z) forming a low dielectric constant insulating layer having a specific dielectric constant lower than the specific dielectric constant of silicon oxide on the first hydrophobic insulating layer having a bydrophilized surface. A semiconductor device manufacturing method which can suppress peel-off of a low dielectric constant insulating layer from an underlying hydrophobic layer is provided.Type: GrantFiled: April 10, 2003Date of Patent: February 17, 2004Assignee: Fujitsu LimitedInventors: Yukio Takigawa, Shun-ichi Fukuyama
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Publication number: 20040002208Abstract: A method of manufacturing a semiconductor device includes the steps of: (X) forming a first hydrophobic insulating layer above a semiconductor substrate; (Y) hydrophilizing a surface of the first hydrophobic insulating layer; and (Z) forming a low dielectric constant insulating layer having a specific dielectric constant lower than the specific dielectric constant of silicon oxide on the first hydrophobic insulating layer having a bydrophilized surface. A semiconductor device manufacturing method which can suppress peel-off of a low dielectric constant insulating layer from an underlying hydrophobic layer is provided.Type: ApplicationFiled: April 10, 2003Publication date: January 1, 2004Applicant: FUJITSU LIMITEDInventors: Yukio Takigawa, Shun-ichi Fukuyama
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Patent number: 6656996Abstract: Resin composition for sealing semiconductor devices, which contains a filler (A) of spherical fused silica having maximum particle size of not larger than 45 &mgr;m and may contain metal impurities having a particle size of not larger than 53 &mgr;m; and a semiconductor device sealed with the resin composition.Type: GrantFiled: May 16, 2000Date of Patent: December 2, 2003Assignees: Sumitomo Bakelite Co. Ltd., Fujitsu LimitedInventors: Yasuaki Tsutsumi, Tetsuya Mieda, Masayuki Tanaka, Toshimi Kawahara, Yukio Takigawa
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Publication number: 20030137052Abstract: A method is provided for manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a set of conducting portions which are electrically connected to each other to have a surface area of no less than 500 &mgr;m2 and which include a wiring having a width of no more than l.0 &mgr;m. The method includes a polishing step (501) for flattening the conducting portions together with the insulating film by chemical mechanical polishing, a chemical cleaning step (502) for cleaning the flattened surface of the insulating film with a cleaning liquid, and a rising step (503) for removing the cleaning liquid using a rinsing liquid. The rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.Type: ApplicationFiled: December 23, 2002Publication date: July 24, 2003Applicant: FUJITSU LIMITEDInventors: Hiroshi Horiuchi, Tamotsu Yamamoto, Yukio Takigawa, Shigeru Suzuki, Nobuaki Santo, Motoshu Miyajima
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Patent number: 6565419Abstract: Disclosed is a method of readily removing particles from a stage, that is, a stage particle removing method for removing particles from a stage that holds a planar workpiece. A resin film is placed on the stage, and collected from the stage. The resin film is coated over at least one surface of the planar workpiece such as a semiconductor wafer or glass substrate. The resin film is brought into contact with the stage. The resin film may not be coated over the planar workpiece itself but may be coated over a dedicated planar piece shaped similarly to the planar workpiece, for example, a thin metallic plate that is very smooth. The used resin film is peeled off from the planar workpiece or dedicated planar piece, and the resin film is coated again. Thus, the planar workpiece or dedicated planar piece can be reused.Type: GrantFiled: February 3, 2000Date of Patent: May 20, 2003Assignees: Advantest Corporation, Fujitsu LimitedInventors: Naoki Nishio, Kazushi Ishida, Yukio Takigawa, Ei Yano