Abstract: A microprocessor with a DMA controller for performing data transfers between a peripheral unit and a memory in response to a transfer request from the peripheral unit. The DMA controller includes a first memory block for storing information necessary to perform a current DMA data transfer and a second memory block for storing information necessary to perform the next DMA data transfer. The second DMA data transfer is initiated after completion of the first data transfer and the information stored in the second memory block is transferred to the first memory block. This process is repeated for all subsequent DMA data transfers. Each section of information stored in the first and second memory blocks includes the number of data transfers to be performed, a memory access address representing the location of the data to be transferred, and control/status information.

Abstract: A data transfer controlling device of a direct memory access controller (DMAC) type includes a transfer number data storage, a transfer number updating decrementer, a data setter for setting predetermined initial data in the transfer number data storage, a terminal counter with a decrementer or an area counter with a decrementer, a memory address register, an address updating section, and a DMA execution control section. The number of times of transfer for the subsequent DMA transfer is automatically set when the number of DMA transfers to be successively executed in response to each DMA transfer request has been completed. Immediately thereafter, the DMA transfer is repeated in response to the subsequent DMA transfer request. When the DMA transfer has been completed to the final data in the DMA transfer source region of a memory, it is placed in an inhibited state. Thus, DMAC can respond to the DMA transfer request issued from a peripheral device at a high speed.

Abstract: A single chip microcomputer includes two kinds of timer circuits which receive a common clock signal. One of the timer circuits generates a first timer signal, and the other generates a second timer signal. When the first timer signal is being reset, the second timer signal is inactive.

Abstract: When DMA transfer for a DMA transfer area is completed, DMA transfer for the next area may be continuously executed or stopped. In addition to this, if there is a need to urgently stop DMA transfer being executed, DMA transfer can be immediately stopped without waiting for the end of DMA transfer currently executed. For continuous DMA transfer for a plurality of DMA transfer areas, the device may be provided with an authorization bit to authorize DMA transfer operation and a next area authorization bit to authorize DMA transfer for the next area and the contents in the next area authorization bit are set to the DMA authorization bit when the terminal counter which counts the number of DMA transfer data reaches the predetermined value due to decrement. Depending on the contents in the DMA authorization bit, DMA transfer may be continued or stopped when the next DMA transfer request is generated.

Abstract: A port output controller for use in a microcomputer for outputting data to a plurality of output terminals in real time, includes a latch circuit for latching data being outputted to the output terminals and a buffer register for storing data to be outputted to the output terminals next to the data being outputted to the output terminals. A timer counter counts an elapsed time after the next data has been latched in the latch circuit and causes the next data stored in the buffer register to be latched into the latch circuit when the counted elapsed time becomes a predetermined data outputting period of time.

Abstract: A data processor comprises a central processing unit, a plurality of register banks used by the central processing unit when the central processing unit executes a given process, an interrupt controller responding to an interrupt request signal to generate an interrupt acknowledge signal and to select a predetermined register bank and also to start an interrupt handling program, a interrupt code generator for generating an interrupt code corresponding to an interrupt request when the interrupt request signal is generated, and an interrupt source register for holding the interrupt code after the interrupt request is acknowledged until a next interrupt request is acknowledged, so that a start address of the interrupt handling program is controlled in accordance with the contents of the interrupt source register.