Patents by Inventor Yumi Hoshino

Yumi Hoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9991386
    Abstract: A method of manufacturing an epitaxial wafer, including a silicon substrate having a surface sliced from single-crystalline silicon and a silicon epitaxial layer deposited on the surface of the silicon substrate, includes an oxygen concentration controlling heat treatment process in which a heat treatment of the epitaxial layer is performed under a non-oxidizing atmosphere after the epitaxial growth such that an oxygen concentration of the surface of the silicon epitaxial layer is set to 1.0×1017 to 12×1017 atoms/cm3 (ASTM F-121, 1979).
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 5, 2018
    Assignee: SUMCO CORPORATION
    Inventors: Toshiaki Ono, Yumi Hoshino
  • Publication number: 20160240677
    Abstract: A method of manufacturing an epitaxial wafer, including a silicon substrate having a surface sliced from single-crystalline silicon and a silicon epitaxial layer deposited on the surface of the silicon substrate, includes an oxygen concentration controlling heat treatment process in which a heat treatment of the epitaxial layer is performed under a non-oxidizing atmosphere after the epitaxial growth such that an oxygen concentration of the surface of the silicon epitaxial layer is set to 1.0×1017 to 12×1017 atoms/cm3 (ASTM F-121, 1979).
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Yumi HOSHINO
  • Patent number: 9362114
    Abstract: A method of manufacturing an epitaxial wafer, including a silicon substrate having a surface sliced from single-crystalline silicon and a silicon epitaxial layer deposited on the surface of the silicon substrate, includes an oxygen concentration controlling heat treatment process in which a heat treatment of the epitaxial layer is performed under a non-oxidizing atmosphere after the epitaxial growth such that an oxygen concentration of the surface of the silicon epitaxial layer is set to 1.0×1017 to 12×1017 atoms/cm3 (ASTM F-121, 1979).
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: June 7, 2016
    Assignee: SUMCO CORPORATION
    Inventors: Toshiaki Ono, Yumi Hoshino
  • Patent number: 8765492
    Abstract: This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 1, 2014
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Takayuki Kihara, Yumi Hoshino
  • Publication number: 20130140752
    Abstract: Provided are a method and a jig for holding a silicon wafer, which are applied to the production of the silicon wafer having {110} or {100} plane as its principal surface, in which the silicon wafer is held while a silicon wafer holding positions are properly defined at wafer edge regions relative to the reference direction as being from the center of the silicon wafer toward <110> in crystal orientation in parallel to the wafer surface. In handling the silicon wafer, generation of contact scratches is suppressed as little as possible, and a fracture which is caused by development of the crack initiating from easily generated contact scratches can be prevented in the silicon wafer, particularly in the silicon wafer having {110} plane as its principal surface.
    Type: Application
    Filed: January 30, 2013
    Publication date: June 6, 2013
    Inventors: Toshiaki Ono, Yumi Hoshino
  • Patent number: 8419001
    Abstract: Provided are a method and a jig for holding a silicon wafer, which are applied to the production of the silicon wafer having {110} or {100} plane as its principal surface, in which the silicon wafer is held while a silicon wafer holding positions are properly defined at wafer edge regions relative to the reference direction as being from the center of the silicon wafer toward <110> in crystal orientation in parallel to the wafer surface. In handling the silicon wafer, generation of contact scratches is suppressed as little as possible, and a fracture which is caused by development of the crack initiating from easily generated contact scratches can be prevented in the silicon wafer, particularly in the silicon wafer having {110} plane as its principal surface.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: April 16, 2013
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Yumi Hoshino
  • Publication number: 20120012983
    Abstract: This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.
    Type: Application
    Filed: March 24, 2010
    Publication date: January 19, 2012
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki Ono, Takayuki Kihara, Yumi Hoshino
  • Publication number: 20100151692
    Abstract: A method of manufacturing an epitaxial wafer, including a silicon substrate having a surface sliced from single-crystalline silicon and a silicon epitaxial layer deposited on the surface of the silicon substrate, includes an oxygen concentration controlling heat treatment process in which a heat treatment of the epitaxial layer is performed under a non-oxidizing atmosphere after the epitaxial growth such that an oxygen concentration of the surface of the silicon epitaxial layer is set to 1.0×1017 to 12×1017 atoms/cm3 (ASTM F-121, 1979).
    Type: Application
    Filed: December 10, 2009
    Publication date: June 17, 2010
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Yumi HOSHINO
  • Publication number: 20100025909
    Abstract: Provided are a method and a jig for holding a silicon wafer, which are applied to the production of the silicon wafer having {110} or {100} plane as its principal surface, in which the silicon wafer is held while a silicon wafer holding positions are properly defined at wafer edge regions relative to the reference direction as being from the center of the silicon wafer toward <110> in crystal orientation in parallel to the wafer surface. In handling the silicon wafer, generation of contact scratches is suppressed as little as possible, and a fracture which is caused by development of the crack initiating from easily generated contact scratches can be prevented in the silicon wafer, particularly in the silicon wafer having {110} plane as its principal surface.
    Type: Application
    Filed: October 12, 2007
    Publication date: February 4, 2010
    Inventors: Toshiaki Ono, Yumi Hoshino