Patents by Inventor Yumiko Iwanami

Yumiko Iwanami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5592097
    Abstract: A load open state detection circuit includes a driver having X and Y terminals between which an inductive load is connected and which receive drive signals, a first transistor whose base is connected to the X terminal and whose collector is connected to a terminal supplied with a predetermined voltage, a second transistor whose base is connected to the Y terminal and whose collector is connected to the terminal supplied with a predetermined voltage and third and fourth transistors having bases thereof connected to input terminals supplied with respective drive signals. A fifth transistor has a base connected to the base of the first transistor, a collector connected to a resistor which is in turn connected to the collector of the first transistor, and an emitter connected to a second resistor which is connected to the emitter of the first transistor.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: January 7, 1997
    Assignee: NEC Corporation
    Inventors: Toshifumi Shimizu, Yumiko Iwanami, Kazuhiro Mori
  • Patent number: 5457391
    Abstract: A load short-circuit state detection circuit has a driver including X and Y terminals between which an inductive load is connected and receiving drive signals. The detection circuit further includes a first transistor whose base is connected to the X terminal and whose collector is supplied with a voltage, a second transistor whose base is connected to the Y terminal and whose collector is also supplied with a voltage, a first constant current circuit connected to an emitter of the first transistor through a first resistor and a second constant current circuit connected to an emitter of the second transistor through a second resistor. A comparator is provided for comparing a voltage of a node between the first resistor and the first constant current circuit with a voltage of a node between the second resistor and the second constant current circuit.
    Type: Grant
    Filed: August 23, 1993
    Date of Patent: October 10, 1995
    Assignee: NEC Corporation
    Inventors: Toshifumi Shimizu, Yumiko Iwanami, Kazuhiro Mori