Abstract: A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.

Abstract: A memory includes: a memory array; a nonvolatile memory circuit suitable for storing a plurality of data sets each including flag information and multi-bit data; a plurality of repair register sets suitable for receiving and storing the multi-bit data included in the data sets whose flag information is marked for repair among the data sets during a boot-up operation; a plurality of setting register sets suitable for storing setting information included in the data sets whose flag information is marked for setting among the data sets during the boot-up operation; and a repair circuit suitable for repairing a defect in the memory array based on the multi-bit data stored in the repair register sets.

Abstract: Disclosed is a semiconductor integrated circuit comprising a master chip including a first buffer circuit coupled to a first power line that is supplied with a first voltage and a first supply circuit that supplies a second voltage, having a lower voltage level than the first voltage, to a first through line in response to a control signal, and a slave chip, coupled to the first through line, including a second buffer circuit coupled to a second power line supplied with the second voltage and a second supply circuit that supplies the second voltage to a second through line in response to the control signal, which indicates whether the master chip and the slave chip are stacked.

Abstract: A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.

Abstract: A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.

Abstract: According to an embodiment, a semiconductor device includes a transmission circuit including first and second transistors coupled in series between a first voltage terminal and a second voltage terminal, and a first common node coupled between the first and second transistors and coupled to a through line, the transmission circuit outputting a signal transferred from an internal circuit to the first common node according to an output control signal; a reception circuit including third and fourth transistors coupled in series between the first voltage terminal and the second voltage terminal, and a second common node coupled between the third and fourth transistors and coupled to the internal circuit, the reception circuit transferring a signal transferred through the through line to the internal circuit according to a first input control signal; and a deterioration acceleration circuit for applying stress to the first and third transistors according to a test signal.

Abstract: According to an embodiment, a semiconductor device includes a transmission circuit including first and second transistors coupled in series between a first voltage terminal and a second voltage terminal, and a first common node coupled between the first and second transistors and coupled to a through line, the transmission circuit outputting a signal transferred from an internal circuit to the first common node according to an output control signal; a reception circuit including third and fourth transistors coupled in series between the first voltage terminal and the second voltage terminal, and a second common node coupled between the third and fourth transistors and coupled to the internal circuit, the reception circuit transferring a signal transferred through the through line to the internal circuit according to a first input control signal; and a deterioration acceleration circuit for applying stress to the first and third transistors according to a test signal.

Abstract: An operating method of a memory device includes: instructing, by a master chip, a first memory chip and a second memory chip to perform a read operation; transferring, by the first memory chip, data stored in the first memory chip to the master chip through a first through-chip channel in response to the read operation instruction, and transferring, by the second memory chip, data stored in the second memory chip to the master chip through a second through-chip channel in response to the read operation instruction; comparing, by the master chip, a phase of the data transferred through the first through-chip channel with a phase of the data transferred through the second through-chip channel; and adjusting a delay value of a data transmission channel of at least one of the first memory chip and the second memory chip based on a result of the comparing.

Abstract: A semiconductor memory device may include a plurality of banks; a plurality of address storage circuits respectively corresponding to the plurality of banks, and suitable for storing refresh addresses of corresponding banks; an output control circuit suitable for, based on a refresh command signal and a test mode signal, generating an output clock and selectively outputting, as output data, a refresh address outputted from any one of the address storage circuits or bank data provided from the banks; an output buffer suitable for outputting the output data to a plurality of data input/output pads based on the output clock; and a strobe signal generation circuit suitable for generating a data strobe signal based on the output clock and outputting the data strobe signal through a data strobe pad.

Abstract: A signal transmitting circuit includes a signal driving unit suitable for driving an output signal in response to an input signal, during an operation mode, and a level shifting unit suitable for shifting a logic level of the output signal in a predetermined cycle, during a standby mode.

Abstract: A semiconductor memory device may include a plurality of banks; a plurality of address storage circuits respectively corresponding to the plurality of banks, and suitable for storing refresh addresses of corresponding banks; an output control circuit suitable for, based on a refresh command signal and a test mode signal, generating an output clock and selectively outputting, as output data, a refresh address outputted from any one of the address storage circuits or bank data provided from the banks; an output buffer suitable for outputting the output data to a plurality of data input/output pads based on the output clock; and a strobe signal generation circuit suitable for generating a data strobe signal based on the output clock and outputting the data strobe signal through a data strobe pad.

Abstract: A data inversion circuit in accordance with an embodiment may include a data input circuit and an inversion latch circuit. The data input circuit may output latch data by latching input data, perform a data inversion by performing a logical operation on the latch data and flag data, generate selective inversion data, and output data composed of multiple bits by aligning the selective inversion data. The inversion latch circuit may generate the flag data by latching inversion data.

Abstract: A signal transmitting circuit includes a signal driving unit suitable for driving an output signal in response to an input signal, during an operation mode, and a level shifting unit suitable for shifting a logic level of the output signal in a predetermined cycle, during a standby mode.

Abstract: An operating method of a memory device includes: instructing, by a master chip, a first memory chip and a second memory chip to perform a read operation; transferring, by the first memory chip, data stored in the first memory chip to the master chip through a first through-chip channel in response to the read operation instruction, and transferring, by the second memory chip, data stored in the second memory chip to the master chip through a second through-chip channel in response to the read operation instruction; comparing, by the master chip, a phase of the data transferred through the first through-chip channel with a phase of the data transferred through the second through-chip channel; and adjusting a delay value of a data transmission channel of at least one of the first memory chip and the second memory chip based on a result of the comparing.

Abstract: A pipe latch circuit includes: a pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.

Abstract: A semiconductor device includes a comparison circuit suitable for comparing a reference voltage and a strobe signal, and generating a first comparison strobe signal. The semiconductor device also includes a reference voltage training circuit suitable for sequentially changing a voltage level of the reference voltage if a training mode is entered, and setting the voltage level of the reference voltage by sensing a duty ratio of the first comparison strobe signal.

Abstract: A semiconductor apparatus may include a through via and a redundancy through via which couple a first chip and a second chip. A transmission circuit may perform a repair operation for the through via with the redundancy through via or supply the redundancy through via with a power supply voltage based on through via defect information.

Abstract: A semiconductor apparatus may include a through via and a redundancy through via which couple a first chip and a second chip. A transmission circuit may perform a repair operation for the through via with the redundancy through via or supply the redundancy through via with a power supply voltage based on through via defect information.

Abstract: A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.

Abstract: A pipe latch circuit includes: a pipe pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.