Abstract: Disclosed herein are image-based object recognition method and system by and in which a learning server performs image-based object recognition based on the learning of environment variable data. The image-based object recognition method includes: receiving an image acquired through at least one camera, and segmenting the image on a per-frame basis; primarily learning labeling results for one or more objects in the image segmented on a per-frame basis; performing primary reasoning by performing object detection in the image through a model obtained as a result of the primary learning; performing data labeling based on the results of the primary reasoning, and performing secondary learning with weights allocated to respective boxes obtained by the primary reasoning and estimated as object regions; and finally detecting one or more objects in the image through a model generated as a result of the secondary learning.

Abstract: Disclosed herein are image-based object recognition method and system by and in which a learning server performs image-based object recognition based on the learning of environment variable data. The image-based object recognition method includes: receiving an image acquired through at least one camera, and segmenting the image on a per-frame basis; primarily learning labeling results for one or more objects in the image segmented on a per-frame basis; performing primary reasoning by performing object detection in the image through a model obtained as a result of the primary learning; performing data labeling based on the results of the primary reasoning, and performing secondary learning with weights allocated to respective boxes obtained by the primary reasoning and estimated as object regions; and finally detecting one or more objects in the image through a model generated as a result of the secondary learning.

Abstract: A method of manufacturing a semiconductor light emitting device, includes: forming a plurality of concave portions on a substrate; injecting silica particles into the plurality of concave portions; and forming a semiconductor layer on the substrate, the semiconductor layer including voids formed in portions of the semiconductor layer, the portions being located above the plurality of concave portions.

Abstract: A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Abstract: A multiprocessor system and method thereof are provided.

Abstract: A multiprocessor system and method thereof are provided.

Abstract: A multiprocessor system and method thereof are provided.

Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Abstract: A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

Abstract: A semiconductor memory device includes ports, data line pairs, where each port associated with one of the data line pairs, sets of address lines, where each port associated with one of the sets of address lines, a shared memory region of a memory cell array, where the shared memory region accessible through the ports, an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports, and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.