Patents by Inventor Yun-Kuei Yang

Yun-Kuei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6706638
    Abstract: A method of forming openings in the dielectric layer. The method includes an ion implantation step to reduce a lateral etching in a chemical vapor etching step, and to provide a high etching selectivity ratio of the dielectric layer to a mask. The dry etching process is partially substituted by the chemical vapor etching step, so that an opening having a straight profile is formed in the dielectric layer. Consequently, problems, such as loss of critical dimension and striation of the opening caused by loss of the mask can be effectively ameliorated.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: March 16, 2004
    Assignee: Winbond Electronics Corp.
    Inventors: Yun-Kuei Yang, Yi-Ming Chang
  • Publication number: 20030003761
    Abstract: A method of forming openings in the dielectric layer. The method includes an ion implantation step to reduce a lateral etching in a chemical vapor etching step, and to provide a high etching selectivity ratio of the dielectric layer to a mask. The dry etching process is partially substituted by the chemical vapor etching step, so that an opening having a straight profile is formed in the dielectric layer. Consequently, problems, such as loss of critical dimension and striation of the opening caused by loss of the mask can be effectively ameliorated.
    Type: Application
    Filed: January 17, 2001
    Publication date: January 2, 2003
    Inventors: Yun-Kuei Yang, Yi-Ming Chang
  • Patent number: 5837426
    Abstract: A photolithographic process which provides reduced line widths or reduced inter-element line spaces for the circuit elements on an IC chip, allowing the IC chip to have a higher degree of integration. The photolithographic process includes a double-exposure process on the same wafer defined by placing either the same photomask at two different positions or by using two photomasks. In the first exposure process, a first selected set of areas on the photoresist layer is exposed through the photomask. In the second exposure process, the photomask is shifted to predetermined positions interleaving or overlapping the positions where the first selected set of exposed areas are formed, or alternatively a second photomask replaces the first photomask. The second photomask has a plurality of patterns arranged in positions correspondingly interleaving or overlapping the positions where the first selected set of exposed areas is formed.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: November 17, 1998
    Assignee: United Microelectronics Corp.
    Inventors: Che-Pin Tseng, Wei-Jiang Lin, Wen-Cheng Tien, Yun-Kuei Yang