Patents by Inventor Yun Kyoung Lee
Yun Kyoung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10115809Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.Type: GrantFiled: April 22, 2015Date of Patent: October 30, 2018Assignee: SK Hynix Inc.Inventors: Yun Kyoung Lee, Jung Ryul Ahn
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Patent number: 9633731Abstract: A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.Type: GrantFiled: March 11, 2016Date of Patent: April 25, 2017Assignee: SK HYNIX INC.Inventors: Jung Ryul Ahn, Yun Kyoung Lee
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Patent number: 9520403Abstract: A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.Type: GrantFiled: July 20, 2015Date of Patent: December 13, 2016Assignee: SK HYNIX INC.Inventors: Jung Ryul Ahn, Yun Kyoung Lee
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Publication number: 20160196877Abstract: A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.Type: ApplicationFiled: March 11, 2016Publication date: July 7, 2016Inventors: Jung Ryul AHN, Yun Kyoung LEE
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Patent number: 9318201Abstract: A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.Type: GrantFiled: December 15, 2014Date of Patent: April 19, 2016Assignee: SK hynix Inc.Inventors: Jung Ryul Ahn, Yun Kyoung Lee
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Patent number: 9274939Abstract: A memory system includes: a memory controller configured to change data to be stored in memory cells according to an address of a weak cell in order to store changed data having a lower program level than a highest program level among a plurality of program levels in peripheral cells adjacent to the weak cell; and a memory device configured to execute a program loop in order to store the changed data in a selected page.Type: GrantFiled: October 25, 2013Date of Patent: March 1, 2016Assignee: SK Hynix Inc.Inventors: Yun Kyoung Lee, Jung Ryul Ahn
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Publication number: 20160012893Abstract: A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.Type: ApplicationFiled: December 15, 2014Publication date: January 14, 2016Inventors: Jung Ryul AHN, Yun Kyoung LEE
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Publication number: 20150325582Abstract: A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Jung Ryul AHN, Yun Kyoung LEE
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Patent number: 9136269Abstract: A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.Type: GrantFiled: October 28, 2014Date of Patent: September 15, 2015Assignee: SK Hynix Inc.Inventors: Jung Ryul Ahn, Yun Kyoung Lee
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Patent number: 9117699Abstract: A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.Type: GrantFiled: October 3, 2013Date of Patent: August 25, 2015Assignee: SK Hynix Inc.Inventors: Jung Ryul Ahn, Yun Kyoung Lee
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Publication number: 20150228767Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.Type: ApplicationFiled: April 22, 2015Publication date: August 13, 2015Inventors: Yun Kyoung LEE, Jung Ryul AHN
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Patent number: 9041124Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.Type: GrantFiled: December 14, 2012Date of Patent: May 26, 2015Assignee: SK Hynix Inc.Inventors: Yun Kyoung Lee, Jung Ryul Ahn
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Publication number: 20150056779Abstract: A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.Type: ApplicationFiled: October 28, 2014Publication date: February 26, 2015Inventors: Jung Ryul AHN, Yun Kyoung LEE
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Publication number: 20150046666Abstract: A memory system includes: a memory controller configured to change data to be stored in memory cells according to an address of a weak cell in order to store changed data having a lower program level than a highest program level among a plurality of program levels in peripheral cells adjacent to the weak cell; and a memory device configured to execute a program loop in order to store the changed data in a selected page.Type: ApplicationFiled: October 25, 2013Publication date: February 12, 2015Applicant: SK hynix Inc.Inventors: Yun Kyoung LEE, Jung Ryul AHN
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Patent number: 8921182Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.Type: GrantFiled: September 5, 2012Date of Patent: December 30, 2014Assignee: SK Hynix Inc.Inventors: Sung-Wook Jung, Yun-Kyoung Lee, Young-Soo Ahn, Tae-Hwa Lee
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Publication number: 20140374810Abstract: A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.Type: ApplicationFiled: October 3, 2013Publication date: December 25, 2014Applicant: SK hynix Inc.Inventors: Jung Ryul AHN, Yun Kyoung LEE
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Patent number: 8901629Abstract: A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.Type: GrantFiled: August 28, 2012Date of Patent: December 2, 2014Assignee: SK Hynix Inc.Inventors: Jung Ryul Ahn, Yun Kyoung Lee
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Publication number: 20140048890Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.Type: ApplicationFiled: December 14, 2012Publication date: February 20, 2014Applicant: SK Hynix Inc.Inventors: Yun Kyoung LEE, Jung Ryul AHN
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Publication number: 20130309849Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.Type: ApplicationFiled: September 5, 2012Publication date: November 21, 2013Inventors: Sung-Wook JUNG, Yun-Kyoung LEE, Young-Sao AHN, Tae-Hwa LEE
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Patent number: 8546788Abstract: Patterns of a nonvolatile memory device include a semiconductor substrate including active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layer is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.Type: GrantFiled: October 19, 2012Date of Patent: October 1, 2013Assignee: Hynix Semiconductor Inc.Inventor: Yun Kyoung Lee