Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract: Provided are a semiconductor package, a semiconductor device provided with the same, and a method of fabricating the same. The semiconductor package may include a package substrate including a central region and a peripheral region, a first semiconductor chip provided on the package substrate, a first connection pattern provided on the central region of the package substrate to connect the package substrate electrically to the first semiconductor chip, at least one second semiconductor chip provided on the peripheral region of the package substrate and between the package substrate and the first semiconductor chip, and a second connection pattern provided on the peripheral region of the package substrate to connect the first semiconductor chip electrically to the second semiconductor chip.

Abstract: A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include a wiring board including a mounting region and a ground region that surrounds the mounting region, a ground pad positioned at the ground region, at least one semiconductor chip mounted at the mounting region of the wiring board, a molding layer covering the semiconductor chip and a first surface of the wiring board and exposing a portion of the ground pad of the ground region of the wiring board, and a shield layer covering the molding layer and electrically connected to the ground pad. The molding layer comprises a plurality of light-sensitive particles positioned in the molding layer and a plurality of conductive particles positioned at a surface of the molding layer. The shield layer is in direct contact with the conductive particles.

Abstract: Provided are a semiconductor package, a semiconductor device provided with the same, and a method of fabricating the same. The semiconductor package may include a package substrate including a central region and a peripheral region, a first semiconductor chip provided on the package substrate, a first connection pattern provided on the central region of the package substrate to connect the package substrate electrically to the first semiconductor chip, at least one second semiconductor chip provided on the peripheral region of the package substrate and between the package substrate and the first semiconductor chip, and a second connection pattern provided on the peripheral region of the package substrate to connect the first semiconductor chip electrically to the second semiconductor chip.

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract: Provided is an apparatus for manufacturing a bonding structure, a bonding structure, and a method of fabricating the same. The bonding structure includes a pad including an upper surface with a first area, a ball adhered to the upper surface of the pad, and a wire extending from the ball. An adhesion surface of the ball adhered to the pad may have substantially the same shape as that of the upper surface of the pad.

Abstract: A method of manufacturing a semiconductor package includes forming a protection layer on a support plate, stacking substrates on the protection layer, electrically connecting the substrates to each other, forming a molding layer on the support plate, and removing the support plate while the protection layer remains on the substrates. The stacked substrates are offset from adjacent substrates.

Abstract: A method of manufacturing a multi-chip package in which a plurality of semiconductor chips are mounted on a single package using a chip-on-chip technique reduces warping due to a difference in coefficients of thermal expansion (CTEs) between a printed circuit board (PCB) and a stacked semiconductor chip. A package on package is manufactured by vertically stacking packages to operate a memory semiconductor chip package and a logic semiconductor chip package in a single system. To improve a non-wet defect of solder balls used to connect packages and minimize the mounting height of the package on package, a protection member formed of an epoxy mold compound (EMC) is formed on the memory semiconductor chip package to only partially expose the solder balls, and the exposed portions of the solder balls are connected to vias formed in a rear surface of the logic semiconductor chip package using a solder ball attaching process.

Abstract: A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

Abstract: A semiconductor package may include a base substrate, a solder resist layer on the base substrate, a first semiconductor chip mounted on the base substrate, and a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip may include at least one end portion protruding from the first semiconductor chip. The solder resist layer may include and a recess portion. The recess portion may be formed in the solder resist layer at a position corresponding to the at least one end portion of the second semiconductor chip.

Abstract: Provided is an apparatus for manufacturing a bonding structure, a bonding structure, and a method of fabricating the same. The bonding structure includes a pad including an upper surface with a first area, a ball adhered to the upper surface of the pad, and a wire extending from the ball. An adhesion surface of the ball adhered to the pad may have substantially the same shape as that of the upper surface of the pad.

Abstract: In a semiconductor device, a semiconductor substrate may include a plurality of first conductive pads. An insulating isolation layer may be on the semiconductor substrate so as to separate the first conductive pads. A package substrate may include a plurality of second conductive pads. A conductive adhesive layer may connect the first conductive pads and the second conductive pads.

Abstract: Multi-stack semiconductor packages and application technologies are provided. The multi-stack semiconductor package may include stacked semiconductor packages which may include a topmost semiconductor package and a bottommost semiconductor package. Each of the unit semiconductor packages may include a substrate, a semiconductor chip formed on the substrate, a molding material filled around the semiconductor chip on the substrate, and an adhesive layer formed on the semiconductor chip and the molding material. The semiconductor chip and the substrate of a semiconductor package may each include conductive vias providing an electrical connection between the semiconductor packages. The substrate of the upper semiconductor package stacked in an upper portion may be directly adhered onto the adhesive layer of the lower semiconductor package stacked in a lower portion.

Abstract: A method of manufacturing a multi-chip package in which a plurality of semiconductor chips are mounted on a single package using a chip-on-chip technique reduces warping due to a difference in coefficients of thermal expansion (CTEs) between a printed circuit board (PCB) and a stacked semiconductor chip. A package on package is manufactured by vertically stacking packages to operate a memory semiconductor chip package and a logic semiconductor chip package in a single system. To improve a non-wet defect of solder balls used to connect packages and minimize the mounting height of the package on package, a protection member formed of an epoxy mold compound (EMC) is formed on the memory semiconductor chip package to only partially expose the solder balls, and the exposed portions of the solder balls are connected to vias formed in a rear surface of the logic semiconductor chip package using a solder ball attaching process.

Abstract: A method of manufacturing a semiconductor package includes forming a protection layer on a support plate, stacking substrates on the protection layer, electrically connecting the substrates to each other, forming a molding layer on the support plate, and removing the support plate while the protection layer remains on the substrates. The stacked substrates are offset from adjacent substrates.

Abstract: A semiconductor wafer includes a plurality of unitary semiconductor chips formed on a semiconductor substrate. Scribe lane region separate the unitary semiconductor chips from each other. Test element group (TEG) pads are configured to apply testing signals for testing respective test elements. A TEG pad is arranged such that an acute angle formed at an intersection of a line extending from portion of a perimeter of the TEG pad and at least a portion of the outer edge of a corresponding scribe lane region is greater than 0° and less than or equal to 60°.

Abstract: In a semiconductor device, a semiconductor substrate may include a plurality of first conductive pads. An insulating isolation layer may be on the semiconductor substrate so as to separate the first conductive pads. A package substrate may include a plurality of second conductive pads. A conductive adhesive layer may connect the first conductive pads and the second conductive pads.