Patents by Inventor Yun-Seok Cho
Yun-Seok Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11771647Abstract: The present invention provides an eye drop formulation in the form of a solution, comprising (2R,3R,4S)-6-amino-4-[N-(4-chlorophenyl)-N-(1H-imidazol-2-ylmethyl)amino]-3-hydroxy-2-methyl-2-dimethoxymethyl-3,4-dihydro-2H-1-benzopyran or a pharmaceutically acceptable salt thereof; propylene glycol as a stabilizing agent; and a pH controlling agent in an aqueous medium, wherein the eye drop formulation has a pH ranging from 4.0 to 5.0. The eye drop formulation of the present invention can contain (2R,3R,4S)-6-amino-4-[N-(4-chlorophenyl)-N-(1H-imidazol-2-ylmethyl)amino]-3-hydroxy-2-methyl-2-dimethoxymethyl-3,4-dihydro-2H-1-benzopyran or a pharmaceutically acceptable salt thereof in a high concentration; and has an excellent stability. In addition, the pharmaceutical product for preventing or treating macular degeneration according to the present invention can be stored for extended periods.Type: GrantFiled: February 18, 2019Date of Patent: October 3, 2023Assignee: HANLIM PHARMACEUTICAL CO., LTD.Inventors: Dong-Yeop Shin, Hu-Seong Kim, Geun-Hyeog Lee, Kyung-Joon Kim, Yun-Seok Cho, Mi-Jin O, Mi-Jung Kim
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Publication number: 20200405634Abstract: The present invention provides an eye drop formulation in the form of a solution, comprising (2R,3R,4S)-6-amino-4-[N-(4-chlorophenyl)-N-(1H-imidazol-2-ylmethyl)amino]-3-hydroxy-2-methyl-2-dimethoxymethyl-3,4-dihydro-2H-1-benzopyran or a pharmaceutically acceptable salt thereof; propylene glycol as a stabilizing agent; and a pH controlling agent in an aqueous medium, wherein the eye drop formulation has a pH ranging from 4.0 to 5.0. The eye drop formulation of the present invention can contain (2R,3R,4S)-6-amino-4-[N-(4-chlorophenyl)-N-(1H-imidazol-2-ylmethyl)amino]-3-hydroxy-2-methyl-2-dimethoxymethyl-3,4-dihydro-2H-1-benzopyran or a pharmaceutically acceptable salt thereof in a high concentration; and has an excellent stability. In addition, the pharmaceutical product for preventing or treating macular degeneration according to the present invention can be stored for extended periods.Type: ApplicationFiled: February 18, 2019Publication date: December 31, 2020Applicant: HANLIM PHARMACEUTICAL CO., LTD.Inventors: Dong-Yeop SHIN, Hu-Seong KIM, Geun-Hyeog LEE, Kyung-Joon KIM, Yun-Seok CHO, Mi-Jin O, Mi-Jung KIM
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Patent number: 10485786Abstract: The present invention provides a pharmaceutical composition for preventing or treating macular degeneration, which comprises benzopyran derivatives substituted with secondary amines including imidazole or pharmaceutically acceptable salts thereof as an active ingredient. The pharmaceutical composition of the present invention may be used in the form of eye drops.Type: GrantFiled: March 30, 2018Date of Patent: November 26, 2019Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Kyu-Yang Yi, Sung-Eun Yoo, Nack-Jeong Kim, Jee-Hee Suh, Choun-Ki Joo, Jun-Sub Choi, Jae-Sik Yang, Geun-Hyeog Lee, Yun-Seok Cho, Jin-Ha Park, Hye-Sung Lee
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Publication number: 20180221343Abstract: The present invention provides a pharmaceutical composition for preventing or treating macular degeneration, which comprises benzopyran derivatives substituted with secondary amines including imidazole or pharmaceutically acceptable salts thereof as an active ingredient. The pharmaceutical composition of the present invention may be used in the form of eye drops.Type: ApplicationFiled: March 30, 2018Publication date: August 9, 2018Applicants: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY, CATHOLIC UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATIONInventors: Kyu-Yang YI, Sung-Eun YOO, Nack-Jeong KIM, Jee-Hee SUH, Choun-Ki JOO, Jun-Sub CHOI, Jae-Sik YANG, Geun-Hyeog LEE, Yun-Seok CHO, Jin-Ha PARK, Hye-Sung LEE
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Publication number: 20140018402Abstract: The present invention provides a pharmaceutical composition for preventing or treating macular degeneration, which comprises benzopyran derivatives substituted with secondary amines including imidazole or pharmaceutically acceptable salts thereof as an active ingredient. The pharmaceutical composition of the present invention may be used in the form of eye drops.Type: ApplicationFiled: March 29, 2011Publication date: January 16, 2014Applicants: CATHOLIC UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION, KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Kyu-Yang Yi, Sung-Eun Yoo, Nack-Jeong Kim, Jee-Hee Suh, Choun-Ki Joo, Jun-Sub Choi, Jae-Sik Yang, Geun-Hyeog Lee, Yun-Seok Cho, Jin-Ha Park, Hye-Sung Lee
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Patent number: 8294207Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.Type: GrantFiled: June 24, 2011Date of Patent: October 23, 2012Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Cho, Yun-Seok Cho, Myung-Ok Kim, Sang-Hoon Park, Young-Kyun Jung
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Patent number: 8169020Abstract: A semiconductor device includes a substrate having trenches, buried bit lines formed in the substrate, and including a metal silicide layer and a metallic layer, wherein the metal silicide layer contacts sidewalls of the trenches and the metallic layer is formed over the sidewalls of the trenches and contacts the metal silicide layer.Type: GrantFiled: December 29, 2009Date of Patent: May 1, 2012Assignee: Hynix Semiconductor Inc.Inventor: Yun-Seok Cho
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Patent number: 8053313Abstract: In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each pillar pattern, and the gate electrode is formed by etching the conductive pattern using the spacer as an etch barrier.Type: GrantFiled: December 23, 2008Date of Patent: November 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Yun-Seok Cho, Sang-Hoon Park, Young-Kyun Jung, Chun-Hee Lee
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Publication number: 20110254081Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.Type: ApplicationFiled: June 24, 2011Publication date: October 20, 2011Applicant: Hynix Semiconductor Inc.Inventors: Sang-Hoon CHO, Yun-Seok CHO, Myung-Ok KIM, Sang-Hoon PARK, Young-Kyun JUNG
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Patent number: 7989292Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.Type: GrantFiled: December 12, 2008Date of Patent: August 2, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Cho, Yun-Seok Cho, Myung-Ok Kim, Sang-Hoon Park, Young-Kyun Jung
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Publication number: 20110101447Abstract: A semiconductor device includes a substrate having trenches, buried bit lines formed in the substrate, and including a metal silicide layer and a metallic layer, wherein the metal silicide layer contacts sidewalls of the trenches and the metallic layer is formed over the sidewalls of the trenches and contacts the metal silicide layer.Type: ApplicationFiled: December 29, 2009Publication date: May 5, 2011Inventor: Yun-Seok Cho
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Patent number: 7910443Abstract: A method for fabricating a semiconductor device includes forming a conductive material layer for forming a gate over a substrate including a cell region and a peripheral region, forming hard mask patterns over the conductive material layer, forming a mask pattern over the resultant structure in the cell region, exposing the peripheral region, trimming the hard mask patterns in the peripheral region, removing the mask pattern, and etching the conductive material layer to form gate patterns using the hard mask patterns.Type: GrantFiled: November 6, 2007Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventor: Yun-Seok Cho
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Patent number: 7906398Abstract: In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.Type: GrantFiled: December 16, 2008Date of Patent: March 15, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Park, Yun-Seok Cho, Sang-Hoon Cho, Chun-Hee Lee
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Patent number: 7851842Abstract: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.Type: GrantFiled: July 23, 2010Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventor: Yun-Seok Cho
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Patent number: 7851293Abstract: A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pillar patterns, forming photoresist patterns above a resultant structure where the SOC layer is filled to expose a region for an isolation trench, etching the SOC layer between the photoresist pattern barriers to expose the region for the isolation trench, and etching the exposed structure to a certain depth forming the isolation trench.Type: GrantFiled: December 12, 2008Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventor: Yun-Seok Cho
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Publication number: 20100283102Abstract: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.Type: ApplicationFiled: July 23, 2010Publication date: November 11, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Yun-Seok CHO
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Patent number: 7829415Abstract: A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.Type: GrantFiled: December 16, 2008Date of Patent: November 9, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yun-Seok Cho, Young-Kyun Jung, Chun-Hee Lee
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Patent number: 7785960Abstract: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.Type: GrantFiled: December 30, 2008Date of Patent: August 31, 2010Assignee: Hynix Semiconductor Inc.Inventor: Yun-Seok Cho
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Publication number: 20090291551Abstract: A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pillar patterns, forming photoresist patterns above a resultant structure where the SOC layer is filled to expose a region for an isolation trench, etching the SOC layer between the photoresist pattern barriers to expose the region for the isolation trench, and etching the exposed structure to a certain depth forming the isolation trench.Type: ApplicationFiled: December 12, 2008Publication date: November 26, 2009Applicant: Hynix Semiconductor Inc.Inventor: Yun-Seok CHO
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Publication number: 20090253254Abstract: In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.Type: ApplicationFiled: December 16, 2008Publication date: October 8, 2009Applicant: Hynix Semiconductor Inc.Inventors: Sang-Hoon PARK, Yun-Seok CHO, Sang-Hoon CHO, Chun-Hee LEE