Abstract: Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

Abstract: The present disclosure provides an image encoder. The image encoder is configured to encode an original image and reduce compression loss. The image encoder comprises an image signal processor and a compressor. The image signal processor is configured to receive a first frame image and a second frame image and generates a compressed image of the second frame image using a boundary pixel image of the first frame image. The image signal processor may include memory configured to store first reference pixel data which is the first frame image. The compressor is configured to receive the first reference pixel data from the memory and generate a bitstream obtained by encoding the second frame image based on a difference value between the first reference pixel data and the second frame image. The image signal processor generates a compressed image of the second frame image using the bitstream generated by the compressor.

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

Abstract: A semiconductor package includes: a first thermal pillar disposed on a package substrate, and having an opening; a first chip stack disposed on the package substrate and in the opening of the first thermal pillar, and including a first lateral surface; a semiconductor chip disposed on the package substrate and in the opening, wherein the semiconductor chip is spaced apart from the first chip stack; and a first heat transfer film disposed between the first thermal pillar and the first lateral surface of the first chip stack.

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip, a second semiconductor chip on a first surface of the first semiconductor chip, and a plurality of conductive pillars on the first surface of the first semiconductor chip and adjacent to at least one side of the second semiconductor chip. The first semiconductor chip includes a first circuit layer adjacent to the first surface of the first semiconductor chip. The second semiconductor chip and the plurality of conductive pillars are connected to the first surface of the first semiconductor chip.

Abstract: An image processing device including a memory; and at least one image signal processor configured to: generate, using a first neural network, a feature value indicating whether to correct a global pixel value sensed during a unit frame interval, and generate a feature signal including the feature value; generate an image signal by merging the global pixel value with the feature signal; split a pixel value included in the image signal into a first sub-pixel value and a second sub-pixel value, split a frame feature signal included in the image signal into a first sub-feature value corresponding to the first sub-pixel value and a second sub-feature value corresponding to the second sub-pixel value, and generate a first sub-image signal including the first sub-pixel value and the first sub-feature value, and a second sub-image signal including the second sub-pixel value and the second sub-feature value; and sequentially correct the first sub-image signal and the second sub-image signal using a second neural netwo

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region.

Abstract: An image processing device including a memory; and at least one image signal processor configured to: generate, using a first neural network, a feature value indicating whether to correct a global pixel value sensed during a unit frame interval, and generate a feature signal including the feature value; generate an image signal by merging the global pixel value with the feature signal; split a pixel value included in the image signal into a first sub-pixel value and a second sub-pixel value, split a frame feature signal included in the image signal into a first sub-feature value corresponding to the first sub-pixel value and a second sub-feature value corresponding to the second sub-pixel value, and generate a first sub-image signal including the first sub-pixel value and the first sub-feature value, and a second sub-image signal including the second sub-pixel value and the second sub-feature value; and sequentially correct the first sub-image signal and the second sub-image signal using a second neural netwo

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region.

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.

Abstract: A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.

Abstract: A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Abstract: The present disclosure provides an image encoder. The image encoder is configured to encode an original image and reduce compression loss. The image encoder comprises an image signal processor and a compressor. The image signal processor is configured to receive a first frame image and a second frame image and generates a compressed image of the second frame image using a boundary pixel image of the first frame image. The image signal processor may include memory configured to store first reference pixel data which is the first frame image. The compressor is configured to receive the first reference pixel data from the memory and generate a bitstream obtained by encoding the second frame image based on a difference value between the first reference pixel data and the second frame image. The image signal processor generates a compressed image of the second frame image using the bitstream generated by the compressor.

Abstract: The present invention provides compositions comprising chimeric polypeptides that bind to free ubiquitin proteins or free ubiquitin-like proteins with high affinity, as well as chimeric polypeptides that bind to both free and conjugated ubiquitin proteins or free and conjugated ubiquitin-like proteins, and methods of using the chimeric polypeptides to determine the amount of free or total ubiquitin or free or total ubiquitin-like proteins in various types of samples.

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.