Abstract: An electronic device includes an internal voltage driving circuit configured to drive an internal voltage to one of first and second power supply voltages based on a driving control signal depending on an operating frequency. The electronic device includes a driving control signal generation circuit configured to generate the driving control signal that sets a level of the internal voltage, by detecting the level of the internal voltage.

Abstract: An electronic device includes a driving control signal generation circuit configured to generate first and second driving control signals and a driving switching control signal. The electronic device also includes a switching control signal driving circuit configured to drive a switching control signal to a first voltage on the basis of the first driving control signal and the driving switching control signal or drive the switching control signal to a second voltage on the basis of the second driving control signal, depending on whether a power-down mode is performed.

Abstract: An electronic device includes an internal voltage driving circuit configured to drive an internal voltage to one of first and second power supply voltages based on a driving control signal depending on an operating frequency. The electronic device includes a driving control signal generation circuit configured to generate the driving control signal that sets a level of the internal voltage, by detecting the level of the internal voltage.

Abstract: An electronic device includes a driving control signal generation circuit configured to generate first and second driving control signals and a driving switching control signal. The electronic device also includes a switching control signal driving circuit configured to drive a switching control signal to a first voltage on the basis of the first driving control signal and the driving switching control signal or drive the switching control signal to a second voltage on the basis of the second driving control signal, depending on whether a power-down mode is performed.

Abstract: According to an embodiment, a semiconductor device comprises a first monitoring pad and a second monitoring pad; a test circuit including an NMOS transistor having a drain and source coupled between a first voltage terminal and a common node, a PMOS transistor having a drain and source coupled between the common node and a second voltage terminal, a first switching element having a first terminal coupled to the common node via a first resistor and a second terminal coupled to the first monitoring pad, and a second switching element having a third terminal coupled to the common node via a second resistor and a fourth terminal coupled to the second monitoring pad; and a test control circuit suitable for controlling the test circuit.

Abstract: According to an embodiment, a semiconductor device comprises a first monitoring pad and a second monitoring pad; a test circuit including an NMOS transistor having a drain and source coupled between a first voltage terminal and a common node, a PMOS transistor having a drain and source coupled between the common node and a second voltage terminal, a first switching element having a first terminal coupled to the common node via a first resistor and a second terminal coupled to the first monitoring pad, and a second switching element having a third terminal coupled to the common node via a second resistor and a fourth terminal coupled to the second monitoring pad; and a test control circuit suitable for controlling the test circuit.

Abstract: A device performing a power gating operation includes a switch control signal generation circuit and a power gating circuit. The switch control signal generation circuit controls an operation that generates a first switch control signal and a second switch control signal from a mode signal based on a comparison result of a first power source voltage and a second power source voltage until a mode register set operation is performed after a power-up period ends. The power gating circuit drives a power source voltage to the first power source voltage or the second power source voltage based on the first switch control signal and the second switch control signal.

Abstract: A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Abstract: A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Abstract: A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Abstract: A data transfer device may include: a global input/output (GIO) driver configured for driving input data and outputting the driven data to a first GIO line, and configured for using a second supply voltage lower than a first supply voltage as a source voltage to drive the input data; and a repeater configured for amplifying data applied to the first GIO line, outputting the amplified data to a second GIO line, and shifting the data applied to the first GIO line to a level of the first supply voltage. The repeater may drive the data applied to the first GIO line to a first node, drive an output of the first node to the second GIO line, and reset the first node to the level of the first supply voltage based on a reset signal before a read operation.

Abstract: A data transfer device may include: a global input/output (GIO) driver configured for driving input data and outputting the driven data to a first GIO line, and configured for using a second supply voltage lower than a first supply voltage as a source voltage to drive the input data; and a repeater configured for amplifying data applied to the first GIO line, outputting the amplified data to a second GIO line, and shifting the data applied to the first GIO line to a level of the first supply voltage. The repeater may drive the data applied to the first GIO line to a first node, drive an output of the first node to the second GIO line, and reset the first node to the level of the first supply voltage based on a reset signal before a read operation.

Abstract: A semiconductor integrated circuit device may include a first electrostatic discharge (ESD) protecting circuit and a second ESD protecting circuit. The first ESD protecting circuit may include at least one resistance changeable device connected between a power voltage line and a data pad to discharge an electrostatic. The second ESD protecting circuit may include at least one resistance changeable device connected between the first ESD protecting circuit and a ground voltage line.

Abstract: A semiconductor integrated circuit device may include a first discharging unit and a second discharging unit. The first discharging unit may be coupled between a first line having a first voltage level and a second line having a second voltage level different from the first voltage level. The first discharging unit may be configured to discharge an electrical over stress (EOS) generated from the first line. The second discharging unit may be coupled between the first line and the second line. The second discharging unit may discharge the EOS in the first line to the second line based on an output signal from the first discharging unit.

Abstract: A voltage controlling circuit may include a first voltage terminal, a second voltage terminal and a plurality of Ovonic threshold switch (OTS) units. The second voltage terminal may have a voltage different from that of the first voltage terminal. The OTS devices may be connected between the first voltage terminal and the second voltage terminal. The OTS units may be serially connected with each other.

Abstract: A voltage controlling circuit may include a first voltage terminal, a second voltage terminal and a plurality of Ovonic threshold switch (OTS) units. The second voltage terminal may have a voltage different from that of the first voltage terminal. The OTS devices may be connected between the first voltage terminal and the second voltage terminal. The OTS units may be serially connected with each other.

Abstract: A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Abstract: A semiconductor integrated circuit device may include a first electrostatic discharge (ESD) protecting circuit and a second ESD protecting circuit. The first ESD protecting circuit may include at least one resistance changeable device connected between a power voltage line and a data pad to discharge an electrostatic. The second ESD protecting circuit may include at least one resistance changeable device connected between the first ESD protecting circuit and a ground voltage line.

Abstract: A semiconductor integrated circuit device may include a first discharging unit and a second discharging unit. The first discharging unit may be coupled between a first line having a first voltage level and a second line having a second voltage level different from the first voltage level. The first discharging unit may be configured to discharge an electrical over stress (EOS) generated from the first line. The second discharging unit may be coupled between the first line and the second line. The second discharging unit may discharge the EOS in the first line to the second line based on an output signal from the first discharging unit.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first switching control signal generation circuit configured to generate a first switching control signal which is enabled in synchronization with a time when a first delay period has passed from a time when a power-down mode is entered. The semiconductor device may include a second switching control signal generation circuit configured to generate a second switching control signal which is enabled during a period from a time when a read operation mode or a write operation mode is entered to a time when a second delay period has passed.