Patents by Inventor Yun-Seung Kang
Yun-Seung Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11804549Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.Type: GrantFiled: December 16, 2022Date of Patent: October 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
-
Publication number: 20230121203Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
-
Patent number: 11557677Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.Type: GrantFiled: November 23, 2020Date of Patent: January 17, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
-
Publication number: 20220216402Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.Type: ApplicationFiled: September 8, 2021Publication date: July 7, 2022Inventors: Hye Ji Yoon, O Ik Kwon, Yun Seung Kang, Sang-Kuk Kim, Gwang-Hyun Baek, Tae Hyung Lee, Su Jin Jeon
-
Publication number: 20210074860Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-seung LEE, Yun-seung KANG, Soung-hee LEE, Sang-gyo CHUNG, Hyun-chul LEE
-
Patent number: 10879398Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.Type: GrantFiled: August 24, 2018Date of Patent: December 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
-
Patent number: 10453698Abstract: Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.Type: GrantFiled: August 22, 2018Date of Patent: October 22, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-gyo Chung, Yun-seung Kang, Soung-hee Lee, Ji-seung Lee, Hyun-chul Lee
-
Publication number: 20190221669Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.Type: ApplicationFiled: August 24, 2018Publication date: July 18, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-seung LEE, Yun-seung KANG, Soung-hee LEE, Sang-gyo CHUNG, Hyun-chul LEE
-
Publication number: 20190198339Abstract: Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.Type: ApplicationFiled: August 22, 2018Publication date: June 27, 2019Inventors: Sang-gyo CHUNG, Yun-seung KANG, Soung-hee LEE, Ji-seung LEE, Hyun-chul LEE
-
Patent number: 9324574Abstract: Methods of forming a pattern in a semiconductor device may be provided. The methods may include sequentially forming a first hard mask layer and a second hard mask layer on an etching target layer including first and second regions, forming a first spacer layer on the second hard mask layer, forming a second hard mask pattern layer by etching the second hard mask layer using the first spacer layer, forming a second spacer layer on a sidewall of the second hard mask pattern layer, forming a first hard mask pattern layer by etching the first hard mask layer using the second spacer layer, and etching the etching target layer using the first hard mask pattern layer.Type: GrantFiled: December 22, 2014Date of Patent: April 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventor: Yun Seung Kang
-
Publication number: 20150255304Abstract: Methods of forming a pattern in a semiconductor device may be provided. The methods may include sequentially forming a first hard mask layer and a second hard mask layer on an etching target layer including first and second regions, forming a first spacer layer on the second hard mask layer, forming a second hard mask pattern layer by etching the second hard mask layer using the first spacer layer, forming a second spacer layer on a sidewall of the second hard mask pattern layer, forming a first hard mask pattern layer by etching the first hard mask layer using the second spacer layer, and etching the etching target layer using the first hard mask pattern layer.Type: ApplicationFiled: December 22, 2014Publication date: September 10, 2015Inventor: Yun Seung KANG
-
Patent number: 8551888Abstract: A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.Type: GrantFiled: September 21, 2011Date of Patent: October 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-seung Kang, Jong-chul Park, Kwang-yong Yang, Sang-sup Jeong, Seok-hyun Lim
-
Patent number: 8419853Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: GrantFiled: November 23, 2009Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
-
Publication number: 20120129349Abstract: A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.Type: ApplicationFiled: September 21, 2011Publication date: May 24, 2012Inventors: Yun-seung Kang, Jong-chul Park, Kwang-yong Yang, Sang-sup Jeong, Seok-hyun Lim
-
Patent number: 8058168Abstract: Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate between the semiconductor pillars may be etched to form a trench region. A dielectric isolation pattern partially filling the trench region may be formed, and dielectric sidewall spacers may be formed on sidewalls of the semiconductor pillars. Metal-semiconductor compound regions may be formed on sidewalls of a portion of the trench region that is not filled by the isolation pattern.Type: GrantFiled: February 18, 2010Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Yun-Seung Kang
-
Publication number: 20100216289Abstract: Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate between the semiconductor pillars may be etched to form a trench region. A dielectric isolation pattern partially filling the trench region may be formed, and dielectric sidewall spacers may be formed on sidewalls of the semiconductor pillars. Metal-semiconductor compound regions may be formed on sidewalls of a portion of the trench region that is not filled by the isolation pattern.Type: ApplicationFiled: February 18, 2010Publication date: August 26, 2010Inventors: Jong-Chul Park, Yun-Seung Kang
-
Patent number: 7745290Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.Type: GrantFiled: July 3, 2007Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Heui Song, Jae-Seung Hwang, Min-Chul Chae, Woo-Jin Cho, Yun-Seung Kang, Young-Mi Lee
-
Patent number: 7682450Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: GrantFiled: July 13, 2006Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
-
Publication number: 20100065912Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-Seung KANG, Eun-Kuk CHUNG, Joon KIM, Jin-Hong KIM, Suk-Chul BANG
-
Patent number: 7585757Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.Type: GrantFiled: June 5, 2006Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang