Abstract: A light emitting pixel includes a first organic light emitting diode (OLED) and a capacitor supplying to the first OLED current generated by an electric charge corresponding to a difference between a first voltage supplied to a first electrode of the capacitor and a second voltage supplied to a second electrode of the capacitor. The light emitting pixel further include a second OLED to supply the first voltage to the first electrode. The light emitting pixel further includes a voltage supply device to supply the first voltage to the first electrode in response to the second voltage.

Abstract: A light emitting pixel includes a first organic light emitting diode (OLED) and a capacitor supplying to the first OLED current generated by an electric charge corresponding to a difference between a first voltage supplied to a first electrode of the capacitor and a second voltage supplied to a second electrode of the capacitor. The light emitting pixel further include a second OLED to supply the first voltage to the first electrode. The light emitting pixel further includes a voltage supply device to supply the first voltage to the first electrode in response to the second voltage.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

Abstract: A light emitting pixel includes a first organic light emitting diode (OLED) and a capacitor supplying to the first OLED current generated by an electric charge corresponding to a difference between a first voltage supplied to a first electrode of the capacitor and a second voltage supplied to a second electrode of the capacitor. The light emitting pixel further include a second OLED to supply the first voltage to the first electrode. The light emitting pixel further includes a voltage supply device to supply the first voltage to the first electrode in response to the second voltage.

Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

Abstract: A non-volatile semiconductor memory device includes a memory array having a cell string. The cell string includes a plurality of normal memory cells, a ground selection transistor gated so as to provide a source voltage to the normal memory cells, at least two dummy cells connected between a normal memory cell on one side end of the cell string and the ground selection transistor, wherein the normal memory cells are configured to store data and the dummy cells are configured to not store data. The memory device also includes a word line selection block which controls normal word lines to gate the normal memory cells and dummy word lines to gate the dummy cells, wherein the dummy word lines are controlled as sequential voltage levels during a program operation to select the normal memory cell on the one side end.

Abstract: Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

Abstract: A digital-to-analog converter (DAC) and a digital-to-analog converting method are provided. The DAC includes a first capacitor, an operation amplifier having a first input terminal connected to the first capacitor, a second input terminal, and an output terminal, where the first input terminal is a (?) input terminal and the second input terminal is a (+) input terminal; and a switching circuit having a plurality of switches each being switched in response to a corresponding switching signal from among a plurality of switching signals. The switching circuit performs switching so that the difference between a first voltage and a second voltage can be stored in the first capacitor connected to the operation amplifier during a first period, and performs switching so that an output signal can be output by reflecting a third voltage in the difference stored in the first capacitor during a second period.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: A digital-to-analog converter outputting an analog data voltage corresponding to n-bit data, includes a chopping amplification unit adapted to receive an upper bit voltage corresponding to upper x bits of the n-bit data and a lower bit voltage corresponding to lower y bits of the n-bit data and to output the analog data voltage. The chopping amplification unit may include a sample and hold capacitor adapted to be charged with the upper bit voltage in a non-inverting mode, and a chopping amplifier adapted to supply the upper bit voltage to the sample and hold capacitor in the non-inverting mode and adapted to output a voltage corresponding to the sum of the upper bit voltage and the lower bit voltage as the analog data voltage in an inverting mode.

Abstract: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of p

Abstract: A light emitting pixel includes a first organic light emitting diode (OLED) and a capacitor supplying to the first OLED current generated by an electric charge corresponding to a difference between a first voltage supplied to a first electrode of the capacitor and a second voltage supplied to a second electrode of the capacitor. The light emitting pixel further include a second OLED to supply the first voltage to the first electrode. The light emitting pixel further includes a voltage supply device to supply the first voltage to the first electrode in response to the second voltage.

Abstract: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of p