Patents by Inventor Yunfei Deng
Yunfei Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12001102Abstract: Disclosed are a backlight module and a display device. The backlight module includes a driving backplate and an optical film on a side of the driving backplate light taking-off. The driving backplate includes a substrate, electronic elements, and an adhesive layer. The electronic elements are disposed on a side of the substrate close to the optical film. The adhesive layer covers the electronic elements and includes first adhesive-dispensed portions. The first adhesive-dispensed portions are in contact with the optical film.Type: GrantFiled: April 27, 2023Date of Patent: June 4, 2024Assignee: TCL CHINA STAR OPTOELECTRONIC TECHNOLOGY CO., LTD.Inventors: Hongzhao Deng, Jing Liu, Yunfei Dai, Linnan Chen
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Patent number: 11994771Abstract: A drive backplate and a display device are provided. The drive backplate includes a substrate, a wiring layer arranged on one side of the substrate, and a reflective layer. The reflective layer and the wiring layer are arranged on the same side of the substrate. The wiring layer includes at least one first type line, and the reflective layer covers the first type line. Each first type line includes at least one first recess, and the reflective layer is partially inside the first recess, so the present application increases a contact area between the reflective layer and the first type line, increases a bonding force between the reflective layer and the wiring layer, reduces a risk of detachment of the reflective layer from the wiring layer, and improves product quality of the display device having the drive backplate.Type: GrantFiled: March 31, 2023Date of Patent: May 28, 2024Assignee: TCL China Star Optoelectronics Technology Co., Ltd.Inventors: Yunfei Dai, Jing Liu, Hongzhao Deng, Linnan Chen
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Patent number: 11223089Abstract: A heat-resistant multi-layer composite lithium-ion battery separator, and coating device and manufacturing method for same. The battery separator comprises a base membrane (12) having two end faces provided with a coating paste, and the end faces of the base membrane (12) are both adhered with a composite layer via the coating paste. The composite layer comprises one, two, or multiple composite films (13). The composite films (13) are adhered and fixed via the coating paste. The coating device is employed during the manufacturing, and comprises a base membrane uncoiling reel (1), a coating roller (2), a composite film uncoiling mechanism, a heating and drying mechanism, and a coiling reel (6). The coating roller (2) is arranged in a one-to-one correspondence to the composite film uncoiling mechanism, and two sets of the coating roller and the composite film uncoiling mechanism are provided on two sides of the base membrane (12).Type: GrantFiled: September 13, 2017Date of Patent: January 11, 2022Assignee: HEBEI GELLEC NEW ENERGY MATERIAL SCIENCE & TECHNOLOGY CO., LTD.Inventors: Feng Xu, Haichao Yuan, Yunfei Deng, Wenxian Ma
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Publication number: 20190267598Abstract: A heat-resistant multi-layer composite lithium-ion battery separator, and coating device and manufacturing method for same. The battery separator comprises a base membrane (12) having two end faces provided with a coating paste, and the end faces of the base membrane (12) are both adhered with a composite layer via the coating paste. The composite layer comprises one, two, or multiple composite films (13). The composite films (13) are adhered and fixed via the coating paste. The coating device is employed during the manufacturing, and comprises a base membrane uncoiling reel (1), a coating roller (2), a composite film uncoiling mechanism, a heating and drying mechanism, and a coiling reel (6). The coating roller (2) is arranged in a one-to-one correspondence to the composite film uncoiling mechanism, and two sets of the coating roller and the composite film uncoiling mechanism are provided on two sides of the base membrane (12).Type: ApplicationFiled: September 13, 2017Publication date: August 29, 2019Inventors: Feng Xu, Haichao Yuan, Yunfei Deng, Wenxian Ma
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Patent number: 9678435Abstract: Aspects of the disclosed techniques relate to techniques for resist simulation in lithography. Local minimal light intensity values are determined for a plurality of sample points in boundary regions of an aerial image of a feature to be printed on a resist coating, wherein each of the local minimal light intensity values represents a minimum light intensity value for an area surrounding one of the plurality of sample points. Based on the local minimal light intensity values, horizontal development bias values for the plurality of sample points are then determined. Finally, resist contour data of the feature are determined based at least on the horizontal development bias values.Type: GrantFiled: September 22, 2014Date of Patent: June 13, 2017Assignee: Mentor Graphics, A Siemens BusinessInventors: Yunfei Deng, Yuri Granik, Dmitry Medvedev, Yuan He, Konstantinos Adam
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Publication number: 20160140278Abstract: Aspects of the disclosed techniques relate to techniques for resist simulation in lithography. Local light power values are determined for a plurality of sample points in boundary regions of an aerial image of a feature to be printed on a resist coating, wherein each of the local light power values represents a light power value for an area surrounding one of the plurality of sample points. Based on the local light power values, a vertical shrinkage function is constructed. Resist contour data of the feature are then computed based at least on resist shrinkage effects modeled using the local light power values and the vertical shrinkage function.Type: ApplicationFiled: January 25, 2016Publication date: May 19, 2016Inventors: Yunfei Deng, Yuri Granik, Dmitry Medvedev, Konstantinos Adam
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Publication number: 20150311122Abstract: Methods for forming abutting FinFET cells with a single dummy gate and continuous fins, and the resulting devices, are disclosed. Embodiments may include forming one or more continuous fins on a substrate, forming gates perpendicular to and over the one or more continuous fins to form a first FinFET cell and a second FinFET cell, and forming source and drain contact lines parallel to and between the gates, wherein a source contact line of the first FinFET cell is adjacent to a drain contact line of the second FinFET cell, and the source contact line and the drain contact line are on opposite sides of a gate.Type: ApplicationFiled: April 28, 2014Publication date: October 29, 2015Applicant: Globalfoundries Inc.Inventors: Mahbub RASHED, Yunfei DENG, Juhan KIM, Jongwook KYE, Suresh VENKATESAN, Subramani KENGERI
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Patent number: 9142513Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.Type: GrantFiled: March 12, 2015Date of Patent: September 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook K E, Roderick Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20150187702Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.Type: ApplicationFiled: March 12, 2015Publication date: July 2, 2015Inventors: Mahbub RASHED, Yuansheng MA, Irene LIN, Jason STEPHENS, Yunfei DENG, Lei YUAN, Jongwook KYE, Rod AUGUR, Shibly AHMED, Subramani KENGERI, Suresh VENKATESAN
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Publication number: 20150108583Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventors: Mahbub Rashed, Johan Kim, Yunfei Deng, Suresh Venkatesan
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Patent number: 9006100Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.Type: GrantFiled: August 7, 2012Date of Patent: April 14, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8975712Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.Type: GrantFiled: May 14, 2013Date of Patent: March 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
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Patent number: 8966423Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.Type: GrantFiled: March 11, 2013Date of Patent: February 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye
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Patent number: 8962483Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.Type: GrantFiled: March 13, 2013Date of Patent: February 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Youngtag Woo, Dinesh Somasekhar, Juhan Kim, Yunfei Deng, Jongwook Kye
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Patent number: 8916441Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.Type: GrantFiled: May 14, 2013Date of Patent: December 23, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan
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Publication number: 20140339647Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively.Type: ApplicationFiled: May 14, 2013Publication date: November 20, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
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Publication number: 20140339610Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.Type: ApplicationFiled: May 14, 2013Publication date: November 20, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan
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Patent number: 8881083Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.Type: GrantFiled: May 1, 2013Date of Patent: November 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yunfei Deng, Lei Yuan, Hidekazu Yoshida, Juhan Kim, Mahbub Rashed, Jongwook Kye
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Publication number: 20140273474Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Youngtag WOO, Dinesh Somasekhar, Juhan Kim, Yunfei Deng, Jongwook Kye
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Publication number: 20140258960Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye