Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

Abstract: A voltage converting apparatus is disclosed. The voltage converting apparatus includes a pulse width modulation (PWM) signal generating circuit, a power transistor, a first inductor, a second inductor and a feedback rectifier. The PWM signal generating circuit receives a feedback power to be an operating power and generates a PWM signal. A first terminal of the power transistor receives an input voltage, and a control terminal of the power transistor receives the PWM signal. The second inductor couples with a voltage on the first inductor and generates a coupling voltage. The feedback rectifier rectifies the coupling voltage to generate a feedback power.

Abstract: A driving circuit of a light emitting diode (LED) including an AC power, a rectifier, a power converter, a waveform sampler, and a control circuit is provided. The AC power provides an AC signal. The rectifier is coupled to the AC power and outputs a driving signal. The power converter is coupled to the rectifier. The power converter includes an LED and outputs a first signal positive correlated with a current passing through the LED. The waveform sampler is coupled between the AC power and the rectifier, and outputs a second signal directly proportional to the AC signal. The control circuit is coupled between the waveform sampler and the power converter, and outputs a control signal to the power converter according to a comparison result between the first signal and the second signal.

Abstract: A voltage converting apparatus is disclosed. The voltage converting apparatus includes a pulse width modulation (PWM) signal generating circuit, a power transistor, a first inductor, a second inductor and a feedback rectifier. The PWM signal generating circuit receives a feedback power to be an operating power and generates a PWM signal. A first terminal of the power transistor receives an input voltage, and a control terminal of the power transistor receives the PWM signal. The second inductor couples with a voltage on the first inductor and generates a coupling voltage. The feedback rectifier rectifies the coupling voltage to generate a feedback power.

Abstract: A constant current driving circuit of a light emitting diode (LED) including a control unit, a buck converter, and a compensation unit is provided. The control unit has an input terminal and an output terminal, and outputs a control signal through the output terminal. The buck converter is coupled to an input power, and is coupled between the output terminal of the control unit and an LED string. The compensation unit is coupled between the LED string and the input terminal of the control unit. The control unit receives a compensation signal of the compensation unit through the input terminal. Besides, a lighting apparatus is also provided.

Abstract: A driving circuit of a light emitting diode (LED) including an AC power, a rectifier, a power converter, a waveform sampler, and a control circuit is provided. The AC power provides an AC signal. The rectifier is coupled to the AC power and outputs a driving signal. The power converter is coupled to the rectifier. The power converter includes an LED and outputs a first signal positive correlated with a current passing through the LED. The waveform sampler is coupled between the AC power and the rectifier, and outputs a second signal directly proportional to the AC signal. The control circuit is coupled between the waveform sampler and the power converter, and outputs a control signal to the power converter according to a comparison result between the first signal and the second signal.

Abstract: A driving circuit of a light emitting diode (LED) capable of receiving a power source to supply a driving current to an LED module is provided. The driving circuit includes a first current path and a second current path. The first current path includes a switch. The switch is disposed between the LED module and a terminal. The switch has a control terminal and receives a control signal through the control terminal so as to control whether the LED module is coupled to the terminal via the switch. The second current path is coupled between the LED module and the terminal. The second current path includes an impedance unit and is coupled to the first current path in parallel.

Abstract: A constant current driving circuit of a light emitting diode (LED) including a control unit, a buck converter, and a compensation unit is provided. The control unit has an input terminal and an output terminal, and outputs a control signal through the output terminal. The buck converter is coupled to an input power, and is coupled between the output terminal of the control unit and an LED string. The compensation unit is coupled between the LED string and the input terminal of the control unit. The control unit receives a compensation signal of the compensation unit through the input terminal. Besides, a lighting apparatus is also provided.

Abstract: A method for seasoning a process chamber is disclosed. The seasoning method includes providing a seasoning film on the interior surfaces of a process chamber, typically after cleaning of the chamber.

Abstract: The present disclosure provides a method, integrated circuit, and interconnect structure utilizing non-metal barrier copper damascene integration. The method is provided for fabricating an interconnect for connecting to one or more front end of line (FEOL) devices. The method includes forming a layer of doped oxide on the one or more FEOL devices and forming a first barrier layer on the layer of doped oxide, the first barrier layer comprising such material as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN). The method further includes forming a plurality of refractory metal plugs in the first barrier layer and the doped oxide layer, forming a low dielectric constant film over the first barrier layer and the plurality of refractory metal plugs, and performing a first etch to create trenches through the low dielectric constant film. The plurality of refractory metal plugs and the first barrier layer perform as an etch-stop.

Abstract: A method for plasma treating an exposed copper surface and dielectric insulating layer in a semiconductor device manufacturing process including providing a semiconductor wafer having a process surface including an exposed copper portion and an exposed dielectric insulating layer portion; plasma treating in a first plasma treatment process, the process surface with a first plasma including ammonia (NH3) and nitrogen (N2) plasma to form a copper nitride layer overlying the exposed copper portion; and, plasma treating in a second plasma treatment process the process surface with a second plasma including oxygen (O2).

Abstract: A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.

Abstract: A method for seasoning a process chamber is disclosed. The seasoning method includes providing a seasoning film on the interior surfaces of a process chamber, typically after cleaning of the chamber.

Abstract: A method for plasma treating an exposed copper surface and dielectric insulating layer in a semiconductor device manufacturing process including providing a semiconductor wafer having a process surface including an exposed copper portion and an exposed dielectric insulating layer portion; plasma treating in a first plasma treatment process, the process surface with a first plasma including ammonia (NH3) and nitrogen (N2) plasma to form a copper nitride layer overlying the exposed copper portion; and, plasma treating in a second plasma treatment process the process surface with a second plasma including oxygen (O2).

Abstract: A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.

Abstract: A method of increasing the cracking threshold of a low-k material layer comprising the following steps. A substrate having a low-k material layer formed thereover is provided. The low-k material layer having a cracking threshold. The low-k material layer is plasma treated to increase the low-k material layer cracking threshold. The plasma treatment including a gas that is CO2, He, NH3 or combinations thereof.

Abstract: A method for forming a low k dielectric material block is provided. In one example, the method includes depositing a low k dielectric layer over a semiconductor substrate and curing the deposited low k dielectric layer. The curing may be performed using a remote plasma process in which an excitation gas is excited in a selected region remote from the deposited low k dieletric layer to carry radiation energy and transfer to the low k dielectric layer when the excitation gas contacts the low k dielectric layer.

Abstract: The present disclosure provides a method, integrated circuit, and interconnect structure utilizing non-metal barrier copper damascene integration. The method is provided for fabricating an interconnect for connecting to one or more front end of line (FEOL) devices. The method includes forming a layer of doped oxide on the one or more FEOL devices and forming a first barrier layer on the layer of doped oxide, the first barrier layer comprising such material as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN). The method further includes forming a plurality of refractory metal plugs in the first barrier layer and the doped oxide layer, forming a low dielectric constant film over the first barrier layer and the plurality of refractory metal plugs, and performing a first etch to create trenches through the low dielectric constant film. The plurality of refractory metal plugs and the first barrier layer perform as an etch-stop.

Abstract: A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.

Abstract: The present disclosure provides a method for forming an intermediate trench layer through low k dielectric material deposition in a damascene process for manufacturing semiconductor devices. After depositing a low k dielectric material block, a curing process is applied to the low k dielectric material block for a predetermined curing time period, wherein after the curing time period, the low k dielectric material block forms a first and second low k dielectric layers so as to make the first low k dielectric layer an intermediate trench layer, thereby eliminating the need of an etch stop layer.