Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: A tiled display device includes two panels and two cover layers respectively disposed on the two panels. The two cover layers include a contact region. A top portion and a bottom portion of the contact region have a height H. One of the two cover layers has a thickness Tn. One of the two panels has a distance Xn between an upper surface of the one of the two panels and the bottom portion of the contact region. The one of the two panels is corresponding to the one of the two cover layers. The height H, the thickness Tn and the distance Xn satisfy the equation: 0<H/(Xn+Tn)<0.8.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Abstract: The power supply system of the present invention includes a wireless electricity transmitter and a wireless electricity receiver transmitting electricity by electromagnetic coupling. The wireless electricity receiver is further connected to a vibrator of a vibrating processing apparatus to transmit electricity thereto. The wireless electricity transmitter has a controller to monitor the operating voltage and the operating current of the transmitter, and alternates the oscillation frequency of the operating voltage according to the phase difference between the operating voltage and the operating current. Thereby, the oscillation frequency may approach the resonance frequency of the vibrator in order to improve the efficiency of electricity transmission. Also, the distance between the wireless electricity transmitter and the wireless electricity receiver can be increased.

Abstract: A battery includes a case, in which a battery module, a battery management system and a junction terminal block are received. The battery module has cell blocks electrically connected in series, and each of the cell blocks has electrodes. The junction terminal block has a plurality of junction terminals to be electrically connected to the electrodes of the cell blocks through a plurality of junction wires respectively. The battery further has an external connector having a plurality of external terminals to be electrically connected to the junction terminals of the junction terminal block through a plurality of external wires. The external terminals of the external connector are electrically connected to the cell blocks through the external wires, the junction terminals of the junction terminal block and the junction wires respectively, so that all the cell blocks are able to be charged individually through the external connector.

Abstract: A system of charging a battery pack with single charger includes a battery module, a main charging module, and a balance charging module. The battery module has a battery pack, and the battery pack has a plurality of cells in series. The main charging module has a main charger. The balance charging module has a balance charger. All the cells of the battery pack of the battery module are charged at the same time by the main charger of the main charging module. After the charging task of the main charging module is completed, the cells of the battery pack of the battery module are charged in sequence by the balance charger of the balance charging module.

Abstract: A system of charging a battery pack with single charger includes a battery module, a main charging module, and a balance charging module. The battery module has a battery pack, and the battery pack has a plurality of cells in series. The main charging module has a main charger. The balance charging module has a balance charger. All the cells of the battery pack of the battery module are charged at the same time by the main charger of the main charging module. After the charging task of the main charging module is completed, the cells of the battery pack of the battery module are charged in sequence by the balance charger of the balance charging module.

Abstract: The power supply system of the present invention includes a wireless electricity transmitter and a wireless electricity receiver transmitting electricity by electromagnetic coupling. The wireless electricity receiver is further connected to a vibrator of a vibrating processing apparatus to transmit electricity thereto. The wireless electricity transmitter has a controller to monitor the operating voltage and the operating current of the transmitter, and alternates the oscillation frequency of the operating voltage according to the phase difference between the operating voltage and the operating current. Thereby, the oscillation frequency may approach the resonance frequency of the vibrator in order to improve the efficiency of electricity transmission. Also, the distance between the wireless electricity transmitter and the wireless electricity receiver can be increased.

Abstract: A ferroelectric field effect transistor (FeFET) device includes a semiconductor substrate and a 3D transistor. The 3D transistor includes drain and source electrodes; a channel structure that includes a channel body and a gate dielectric layer; and a gate electrode that is disposed on the gate dielectric layer and that is electrically isolated from the drain and source electrodes. The channel body is disposed between and connected to the drain and source electrodes. The gate dielectric layer covers the channel body, is made of crystalline hafnium zirconium oxide, and has a thickness ranging from 2 nm to 5 nm. The FeFET device has an on/off current ratio that is greater than 5×104.

Abstract: A ferroelectric field effect transistor (FeFET) device includes a semiconductor substrate and a 3D transistor. The 3D transistor includes drain and source electrodes; a channel structure that includes a channel body and a gate dielectric layer; and a gate electrode that is disposed on the gate dielectric layer and that is electrically isolated from the drain and source electrodes. The channel body is disposed between and connected to the drain and source electrodes. The gate dielectric layer covers the channel body, is made of crystalline hafnium zirconium oxide, and has a thickness ranging from 2 nm to 5 nm. The FeFET device has an on/off current ratio that is greater than 5×104.

Abstract: A method for forming a semiconductor device structure is provided that includes forming an oxide layer over a substrate and forming a semiconductor layer over the oxide layer. The method includes patterning the semiconductor layer to form a fin structure over the oxide layer and removing a portion of the fin structure to form a U-shaped trench in the fin structure. The method also includes forming a gate structure on the U-shaped trench.

Abstract: A method for forming a semiconductor device structure is provided that includes forming an oxide layer over a substrate and forming a semiconductor layer over the oxide layer. The method includes patterning the semiconductor layer to form a fin structure over the oxide layer and removing a portion of the fin structure to form a U-shaped trench in the fin structure. The method also includes forming a gate structure on the U-shaped trench.

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an oxide layer formed over a substrate and a fin structure formed over the oxide layer. The fin structure is made of a semiconductor layer, and the semiconductor layer includes a first portion, a second portion and a third portion. The second portion is between the first portion and the third portion. The first portion, the second portion and the third portion construct a U-shaped trench, and the second portion is below the U-shaped trench. The FinFET device structure further includes a gate structure formed in the U-shaped trench.

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an oxide layer formed over a substrate and a fin structure formed over the oxide layer. The fin structure is made of a semiconductor layer, and the semiconductor layer includes a first portion, a second portion and a third portion. The second portion is between the first portion and the third portion. The first portion, the second portion and the third portion construct a U-shaped trench, and the second portion is below the U-shaped trench. The FinFET device structure further includes a gate structure formed in the U-shaped trench.

Abstract: A junction-less transistor having an reverse polarity structure includes a substrate, a semiconductor body, a gate and a gate insulation layer. The substrate has a first polarity. The semiconductor body is disposed on the substrate, and includes a drain, a source and a channel section connected between the drain and the source. The gate covers one side of the channel section away from the substrate. The semiconductor body has a second polarity opposite to the first polarity. With the semiconductor body and the substrate respectively having the opposite second polarity and first polarity, a leakage current can be reduced while also lowering element production costs.

Abstract: A single-wire dimming method is provided in the present invention. The method is adapted for a lamp with a first color light source and a second color light source. The method includes: providing a dimming control interface, wherein the power voltage is chopped when the dimming control interface is operated; dividing a period of the power voltage into a first phase period, a second phase period and a third phase period; chopping the power voltage at the first phase period when a user adjust the dimming control interface to turn on a first color light; chopping the power voltage at the second phase period when a user adjust the dimming control interface to turn on a second color light; chopping the power voltage at the third phase period when a user adjust the dimming control interface to turn on a mix color light, wherein the mix color light is to combine the first color light and the second color light.