Abstract: Provided is a method for preventing or treating a liver disease, including administering a therapeutically effective amount of pharmaceutical composition to a subject in need, and the pharmaceutical composition includes the isothiocyanate structural modified compound and a pharmaceutically acceptable carrier thereof.

Abstract: A method of making a semiconductor device includes forming a circuit layer over a substrate. The method further includes depositing an insulator over the substrate. The method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. The method further includes filling the test line trench to define a test line electrically connected to the circuit layer. The method further includes filling the first trench and the second trench to define a capacitor.

Abstract: The present invention relates a method for vaccinating a mammal to produce an antibody against Enterobacteriaceae infection caused by Klebsiella pneumoniae, Salmonella typhi, or E. coli in central nervous system and/or peripheral blood circulation, which comprises administering an effective amount of an OmpK36/homologues or its derivatives to the mammal.

Abstract: Disclosed are a test kit and method for sensitively and rapidly detecting Klebsiella pneumoniae serotype K1. By using immunochromatographic test, the test kit can sensitively, rapidly and specifically identify whether specimens contain Klebsiella pneumoniae serotype K1. The sensitivity of the test kit preferably attains 1.4×105 cfu/50?.

Abstract: A testing device for portable electronic devices includes a processor storing test programs corresponding to various portable electronic devices, a control module connected to the processor, and a testing apparatus connected to the control module and connecting to tested portable electronic devices. The processor directs the control module and the testing apparatus to test portable electronic devices according to predetermined test programs in a main control mode, and the control module cooperates with the testing apparatus to test portable electronic devices and directs the processor to select test programs according to the tested portable electronic device in a subsidiary control mode.

Abstract: A polysilicon layer is formed on a semiconductor substrate followed by performing a collimator physical vapor deposition (PVD) process to form a titanium nitride layer on the polysilicon layer. A rapid thermal nitridation (RTN) process is then performed to tighten the structure of the titanium nitride layer. Finally, a silicide layer is formed on the barrier layer. By using the titanium nitride layer, the interface between the silicide layer and the polysilicon layer is effective prevented from occurring a spike.

Abstract: The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

Abstract: The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of the capacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

Abstract: A parallel processing architecture of run length codes in an image processing system wherein the run-length codes are represented by the run-start addresses and the run-end addresses of black runs. The image data is loaded into this processing architecture by unit of words. A run detector in the parallel processing architecture detects if there are run-start or run-end bits in a word. When there are run-start bits or run-end bits present in a word, this parallel architecture employs a run-start row address generator and a run-end row address generator, which are all logic circuits and comprise a data flow hardware architecture, to generate run-start row addresses and run-end row addresses in parallel without the CPU intervening. A ripple counter is utilized to derive the crossing count parameter by counting the total number of black runs in a row of image data.