Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.

Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.

Abstract: A display panel and a display device are provided. The display panel has a first region and a second region. A finger structure of a pixel unit located in the first region has one extending direction, and a finger structure of a pixel unit located in the second region has at least one extending direction. In particular, a size of the pixel unit in the first region is larger than a size of the pixel unit in the second region.

Abstract: A display panel includes a TFT substrate, which includes a substrate, a plurality of scan lines, a plurality of data lines, and a first intermediate layer. The scan lines are disposed on the substrate along a first direction, and the scan lines are intersected with the data lines to define a plurality of sub-pixel units. The sub-pixel units include a first sub-pixel unit and a second sub-pixel unit. The first sub-pixel unit has a first light transmission area and a first component installation area, and the second sub-pixel unit has a second light transmission area and a second component installation area. The first intermediate layer is disposed on the substrate and has an opening. The opening is at least partially overlapped with the first light transmission area, and is at least partially overlapped with the second light transmission area.

Abstract: A display panel includes a TFT substrate, which includes a substrate, a plurality of scan lines, a plurality of data lines, and a first intermediate layer. The scan lines are disposed on the substrate along a first direction, and the scan lines are intersected with the data lines to define a plurality of sub-pixel units. The sub-pixel units include a first sub-pixel unit and a second sub-pixel unit. The first sub-pixel unit has a first light transmission area and a first component installation area, and the second sub-pixel unit has a second light transmission area and a second component installation area. The first intermediate layer is disposed on the substrate and has an opening. The opening is at least partially overlapped with the first light transmission area, and is at least partially overlapped with the second light transmission area.

Abstract: An element substrate is provided, including a substrate, a metal layer, a planarization layer and a first conductive layer. The metal layer is disposed on the substrate. The planarization layer is located on the metal layer, wherein the planarization layer includes a contact hole, the contact hole has a continuous wall and a bottom, the bottom exposes the metal layer, and the bottom of the contact hole has a first width. The first conductive layer is located on the planarization layer, wherein the first conductive layer includes an opening, the opening exposes the contact hole, and the opening has a second width above the contact hole, wherein the relationship of the first width and the second width is modified to decrease illumination loss and to prevent problems of shot-circuiting and insufficient capacitance.

Abstract: A display panel comprising a substrate, a plurality of gate lines, source lines, semiconductor layers and light shielding layers is provided. The gate lines are disposed on the substrate in parallel. The source lines are disposed on the substrate in parallel. The gate lines and the source lines are intercrossed to define a plurality of pixel areas. The semiconductor layers are disposed on the corresponding pixel areas, and each semiconductor layer includes at least one channel region overlapping each gate line. The slight shielding layers are located between the channel regions and the substrate. In a normal direction of the substrate, one of the gate lines is overlapped by two of the light shielding layers, and one of the light shielding layers overlaps even number of the source lines.

Abstract: An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer has a first edge in a first direction. The planarization layer is located on the metal layer. The planarization layer includes a contact hole. The contact hole has a contiguous wall and a bottom side. The metal layer is exposed in the bottom side. A contour line of the contiguous wall on a vertical plane is a curved line. The first edge corresponds vertically with a critical point on the contour line. The slope of a tangent line on the critical point of the contour line is between 0.087 to 0.364.

Abstract: An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer has a first edge in a first direction. The planarization layer is located on the metal layer. The planarization layer includes a contact hole. The contact hole has a contiguous wall and a bottom side. The metal layer is exposed in the bottom side. A contour line of the contiguous wall on a vertical plane is a curved line. The first edge corresponds vertically with a critical point on the contour line. The slope of a tangent line on the critical point of the contour line is smaller than 0.176.

Abstract: An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer has a first edge in a first direction. The planarization layer is located on the metal layer. The planarization layer includes a contact hole. The contact hole has a contiguous wall and a bottom side. The metal layer is exposed in the bottom side. A contour line of the contiguous wall on a vertical plane is a curved line. The first edge corresponds vertically with a critical point on the contour line. The slope of a tangent line on the critical point of the contour line is between 0.087 to 0.364.

Abstract: An element substrate is provided, including a substrate, a metal layer, a planarization layer and a first conductive layer. The metal layer is disposed on the substrate. The planarization layer is located on the metal layer, wherein the planarization layer includes a contact hole, the contact hole has a continuous wall and a bottom, the bottom exposes the metal layer, and the bottom of the contact hole has a first width. The first conductive layer is located on the planarization layer, wherein the first conductive layer includes an opening, the opening exposes the contact hole, and the opening has a second width above the contact hole, wherein the relationship of the first width and the second width is modified to decrease illumination loss and to prevent problems of shot-circuiting and insufficient capacitance.

Abstract: An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer has a first edge in a first direction. The planarization layer is located on the metal layer. The planarization layer includes a contact hole. The contact hole has a contiguous wall and a bottom side. The metal layer is exposed in the bottom side. A contour line of the contiguous wall on a vertical plane is a curved line. The first edge corresponds vertically with a critical point on the contour line. The slope of a tangent line on the critical point of the contour line is smaller than 0.176.

Abstract: A display panel comprising a substrate, a plurality of gate lines, source lines, semiconductor layers and light shielding layers is provided. The gate lines are disposed on the substrate in parallel. The source lines are disposed on the substrate in parallel. The gate lines and the source lines are intercrossed to define a plurality of pixel areas. The semiconductor layers are disposed on the corresponding pixel areas, and each semiconductor layer includes at least one channel region overlapping each gate line. The slight shielding layers are located between the channel regions and the substrate. In a normal direction of the substrate, one of the gate lines is overlapped by two of the light shielding layers, and one of the light shielding layers overlaps even number of the source lines.

Abstract: A thin film transistor substrate is provided. The TFT substrate comprises a substrate, a first metal layer, a first insulating layer, a channel layer, a second insulating layer and a gate layer. The first metal layer is disposed on the substrate, and comprises a first portion and a second portion which are separated from each other. The first insulating layer is disposed on the first metal layer. The channel layer is disposed on the first insulating layer. The second insulating layer is disposed on the channel layer. The gate layer is disposed on the second insulating layer. The first portion and the second portion of the first metal layer partially overlap the channel layer.

Abstract: A light emitting system includes a light emitting device having a forward voltage, and an optical power control device. The optical power control device includes a control signal module and a current controller. The control signal module generates a control signal according to the forward voltage, and the current controller permits flow of a driving current through the light emitting device according to the control signal.

Abstract: A light emitting system includes a light emitting device having a forward voltage, and an optical power control device. The optical power control device includes a control signal module and a current controller. The control signal module generates a control signal according to the forward voltage, and the current controller permits flow of a driving current through the light emitting device according to the control signal.

Abstract: An autostereoscopic display apparatus is provided. The autostereoscopic display apparatus includes a liquid-crystal panel and a barrier cell. The barrier cell includes a first substrate, a second substrate, and a liquid-crystal layer. The first substrate includes a first electrode. The second substrate includes a second electrode and a third electrode, wherein the second and third electrodes are separated from each other. The liquid-crystal layer is disposed between the first and second substrates. A black region between the first and third electrodes is formed when a first voltage is applied to the first and second electrodes and a second voltage is applied to the third electrode.

Abstract: An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.